IRQ Block User Interrupt Request (0x40) - 4.1 English

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)
Document ID
PG195
Release Date
2023-11-24
Version
4.1 English
Table 1. IRQ Block User Interrupt Request (0x40)
Bit Index Default Access Type Description
[NUM_USR_INT-1:0] ‘h0 RO

user_int_req

User Interrupt Request

This register reflects the interrupt source AND’d with the enable mask register.