The Root Port Model, illustrated in the previous figure, consists of these blocks:
- dsport (Root Port)
- usrapp_tx
- usrapp_rx
- usrapp_com (Verilog only)
The usrapp_tx and usrapp_rx blocks interface with the dsport block for transmission and reception of TLPs to/from the EndPoint DUT. The Endpoint DUT consists of the DMA Subsystem for PCIe.
The usrapp_tx block sends TLPs to
the dsport block for transmission across the PCI Express Link to the Endpoint DUT. In turn, the Endpoint DUT device
transmits TLPs across the PCI Express Link to the
dsport block, which are subsequently passed to the usrapp_rx block. The dsport and core are responsible for
the data link layer and physical link layer processing when communicating across the
PCI Express logic. Both usrapp_tx and usrapp_rx utilize the
usrapp_com block for shared functions, for
example, TLP processing and log file outputting.
PIO write and read are initiated by usrapp_tx.
The DMA Subsystem for PCIe uses the 7 series Gen2 Integrated Block for PCIe, the 7 series Gen3 Integrated Block for PCIe, the AMD UltraScale™ Devices Gen3 Integrate Block for PCIe, and the AMD UltraScale+™ Devices Integrate Block for PCIe. See the “Test Bench” chapter in the appropriate guide:
- 7 Series FPGAs Integrated Block for PCI Express LogiCORE IP Product Guide (PG054)
- Virtex 7 FPGA Integrated Block for PCI Express LogiCORE IP Product Guide (PG023)
- UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)
- UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213)