Constraining the Subsystem - 4.1 English - PG195

DMA/Bridge Subsystem for PCI Express Product Guide (PG195)
Document ID
PG195
Release Date
2024-12-18
Version
4.1 English

This section contains information about constraining the subsystem in the AMD Vivado™ Design Suite.

Required Constraints

The DMA/Bridge Subsystem for PCI Express® requires the specification of timing and other physical implementation constraints to meet specified performance requirements for PCI Express. These constraints are provided in a Xilinx Design Constraints (XDC) file. Pinouts and hierarchy names in the generated XDC correspond to the provided example design.

Important: If the example design top file is not used, copy the IBUFDS_GTE3 (for UltraScale+ IBUFDS_GTE4) instance for the reference clock, IBUF Instance for sys_rst and also the location and timing constraints associated with them into your local design top.

To achieve consistent implementation results, an XDC containing these original, unmodified constraints must be used when a design is run through the AMD tools. For additional details on the definition and use of an XDC or specific constraints, see Vivado Design Suite User Guide: Using Constraints (UG903).

Constraints provided with the integrated block solution have been tested in hardware and provide consistent results. Constraints can be modified, but modifications should only be made with a thorough understanding of the effect of each constraint. Additionally, support is not provided for designs that deviate from the provided constraints.

Device, Package, and Speed Grade Selections

The device selection portion of the XDC informs the implementation tools which part, package, and speed grade to target for the design.

Important: Because Gen2 and Gen3 Integrated Block for PCIe cores are designed for specific part and package combinations, this section should not be modified.

The device selection section always contains a part selection line, but can also contain part or package-specific options. An example part selection line follows:

CONFIG PART = XCKU040-ffva1156-3-e-es1

Clock Frequencies, Clock Management, and Clock Placement

For detailed information about clock requirements, see the respective product guide listed below:
  • 7 Series FPGAs Integrated Block for PCI Express LogiCORE IP Product Guide (PG054)
  • Virtex 7 FPGA Integrated Block for PCI Express LogiCORE IP Product Guide (PG023)
  • UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156)
  • UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213)

Banking

This section is not applicable for this IP subsystem.

Transceiver Placement

This section is not applicable for this IP subsystem.

I/O Standard and Placement

This section is not applicable for this IP subsystem.