Timing Closure - 2023.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.1 English

Timing closure consists of the design meeting all timing requirements. It is easier to reach timing closure if you have the right HDL and constraints for synthesis. In addition, it is important to iterate through the synthesis stages with improved HDL, constraints, and synthesis options, as shown in the following figure.

Figure 1. Design Methodology for Rapid Convergence

To successfully close timing, follow these general guidelines:

  • When initially not meeting timing, evaluate timing throughout the flow.
  • Focus on worst negative slack (WNS) of each clock as the main way to improve total negative slack (TNS).
  • Review large worst hold slack (WHS) violations (<-1 ns) to identify missing or inappropriate constraints.
  • Revisit the trade-offs between design choices, constraints, and target architecture.
  • Know how to use the tool options and Xilinx® design constraints (XDC).
  • Be aware that the tools do not try to further improve timing (additional margin) after timing is met.

The following sections provide recommendations for reviewing the completeness and correctness of the timing constraints using methodology design rule checks (DRCs) and baselining, identifying the timing violation root causes, and addressing the violations using common techniques.

Note: Timing results after synthesis use estimated net delays and not the actual routing delays. To get the final timing results, run implementation and then check the Report Timing Summary.