When you need to add extra margin on the timing paths of a clock or
between two clocks, you must use the set_clock_uncertainty command. This is also the best and safest way to
over-constrain a portion of a design without modifying the actual clock edges and the
overall clocks relationships. The clock uncertainty defined by you is additive to the
jitter computed by the Vivado tools, and can be
specified separately for setup and hold analysis.
For example, the margin on all intra-clock paths of the design clock
clk0 needs to be tightened by 500 ps to make the
design more robust to noise for both setup and hold:
set_clock_uncertainty -from clk0 -to clk0 0.500If you specify additional uncertainty between two clocks, the constraint
must be applied in both directions (assuming data flows in both directions). The example
below shows how to increase the uncertainty by 250 ps between clk0 and clk1 for setup only:
set_clock_uncertainty -from clk0 -to clk1 0.250 -setup
set_clock_uncertainty -from clk1 -to clk0 0.250 -setup