Global Constraints Between Clocks in Both Directions - 2023.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.1 English

When there is no need to limit the maximum latency, the clock groups can be used. Following is an example to ignore paths between clkA and clkB:

set_clock_groups -asynchronous -group clkA -group clkB

When two master clocks and their respective generated clocks form two asynchronous domains between which all the paths are properly synchronized, the clock groups constraint can be applied to several clocks at once:

set_clock_groups -asynchronous \
-group {clkA clkA_gen0 clkA_gen1 …} \
-group {clkB clkB_gen0 clkB_gen1 …}

Or simply:

set_clock_groups -asynchronous \
-group [get_clocks -include_generated_clock clkA] \
-group [get_clocks -include_generated_clock clkB]