Creating an Output Clock - 2023.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2023-06-07
Version
2023.1 English

An effective way to forward a clock out of a device for clocking devices external to the device, is to use an ODDR component. By tying one of the inputs High and the other Low, you can easily create a well controlled clock in terms of phase relationship and duty cycle (for example, by holding D1 to 0 and the D2 pin to 1, you can achieve a 180 degree phase shift). By utilizing the set/reset and clock enable, you also have control over stopping the clock and holding it at a certain polarity for sustained amounts of time.

If further phase control is necessary for an external clock, an MMCM or PLL can be used with external feedback compensation and/or coarse or fine grained, fixed or variable phase compensation. This allows great control over clock phase and propagation times to other devices simplifying external timing requirements from the device.