Low Fanout Clocks - 2023.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.1 English

In most cases, a low fanout clock is a clock net that is connected to less than 5,000 clock pins, which are placed in 3 or fewer horizontally adjacent clock regions. The clock routing, clock root, and clock distribution are all contained within the localized area.

In some cases, the placer is expected to identify a low fanout clock but fails. This can be caused by design size, device size, or physical XDC constraints, such as a LOC constraint or Pblock, which prevent the placer from placing the loads in a local area. To address this issue, you might need to guide the tool by manually creating a Pblock or modifying the existing physical constraints.

Clocks driven by BUFG_GTs are an example of a low fanout clock. The Vivado placer automatically identifies these clock nets and contains the loads to the clock regions adjacent to the GT interface. The following figure shows a low fanout clock contained in two clock regions with the BUFG_GT driver shown in red.

Tip: To contain a low fanout clock to a single clock region, you can use the CLOCK_LOW_FANOUT XDC constraint.
Figure 1. Low Fanout Clock Contained in Two Clock Regions