Synchronous - 2023.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2023-06-07
Version
2023.1 English

Clock relationships are synchronous when two clocks have a fixed phase relationship. This is the case when two clocks share the following:

  • Common circuitry (common node)
  • Primary clock (same initial phase)