Auto-Pipelining Considerations - 2023.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2023-06-07
Version
2023.1 English

The auto-pipelining feature allows the placer to determine the number of required pipeline stages and their optimal location, which helps timing closure across interface boundaries. You can enable this feature by setting up the auto-pipelining mode of the AXI Register Slice core or by applying the auto-pipelining HDL attribute or XDC constraints for data buses. Because the insertion is timing-driven, always be sure to apply proper timing constraints on the targeted paths. For more information, see this link in the Vivado Design Suite User Guide: Implementation (UG904).

The following example shows auto-pipelining applied on the interface between the module data01 and data12. The output from data01 consists of registers with no control sets.

Figure 1. Simple Data Flow Connections Between Modules Generated by Your Tool

Following is the RTL code for this example. The autopipeline_module attribute is applied on the hierarchical module data01, and the autopipeline_group/autopipeline_limit/autopipeline_include attributes are applied on the nets directly driven by the Q pins of the registers.

data_reg_ap #( .C_DATA_WIDTH(C_DATA_WIDTH)) data01 (
.clk (clk),
.datain (shinreg),
.datareg (d1)
);

data_reg #( .C_DATA_WIDTH(C_DATA_WIDTH)) data12 (
.clk (clk),
.datain (d1),
.datareg (d2)
);

(* autopipeline_module="yes" *)
module data_reg_ap # (
parameter integer C_DATA_WIDTH = 32
)
( input wire clk,
input wire [C_DATA_WIDTH-1:0] datain,
(* autopipeline_group="fwd",autopipeline_limit=24 *)
output reg [C_DATA_WIDTH-1:0] datareg
);

always @(posedge clk) begin
datareg <= datain;
end
endmodule

Following are the XDC constraints for this example, which is an alternative approach to using attributes in the RTL code.

# It's suggested to add the USER_SLR_ASSIGNMENT property at the module 
#level to ensure better logic clustering with its driver and load, see UG912 
#for more details on this property
set_property USER_SLR_ASSIGNMENT APSRC [get_cells data01]
set_property USER_SLR_ASSIGNMENT APDST [get_cells data12]

set_property AUTOPIPELINE_MODULE TRUE [get_cells data01]
set_property AUTOPIPELINE_GROUP WBUS [get_nets -of [get_pins -filter REF_PIN_NAME==Q -of [get_cells data01/*]]]
set_property AUTOPIPELINE_LIMIT 10 [get_nets -of [get_pins -filter REF_PIN_NAME==Q -of [get_cells data01/*]]]