Defining Timing Constraints - 2023.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID: UG949
Release Date: 2023-06-07
Version: 2023.1 English

Introduction
About the UltraFast Design Methodology
Using This Guide
Using the UltraFast Design Methodology Checklist
Using the UltraFast Design Methodology DRCs
Using the UltraFast Design Methodology System-Level Design Flow Diagram
Understanding UltraFast Design Methodology Concepts
Creating and Implementing a Hardware Design
Maximizing Impact Early in the Development Cycle
Validating at Each Design Stage
Taking Advantage of Rapid Validation
Using the Vivado Design Suite
Managing Vivado Design Suite Sources with a Revision Control System
Upgrading to New Vivado Design Suite Releases
Accessing Additional Documentation and Training
Board and Device Planning
PCB Layout Recommendations
Aligning with Physical Components on the PCB
Power Distribution System
Thermal Solution Considerations
PCB Design Considerations
Device Power Aspects and System Dependencies
Power Supply Paths on Devices
Power Types
Power-On
Startup Power
Static Power
Dynamic Power
Factors Impacting Power
Environmental Factors Impacting Power
Power Rail Consolidation Impacting Power
Power Models Accuracy
Device Power and the Overall System Design Process
Worst Case Power Analysis
Clock Resource Planning and Assignment
I/O Planning Design Flows
Types of Vivado Design Suite Projects for I/O Planning
Pre-RTL I/O Planning
Netlist-Based I/O Planning
Identifying Pin Compatible Devices
Pin Assignment
Using AMD Tools in Pinout Selection
Required Information
Pinout Selection
General Pinout Selection Guidelines
Configuration Pins
Memory Interfaces
Gigabit Transceivers (GTs)
High Speed I/O
Internal VREF and DCI Cascade Constraints
Interface Bandwidth Validation
Designing with SSI Devices
SSI Pinout Considerations
Super Logic Region (SLR)
SLR Nomenclature
Master Super Logic Region
Silicon Interposer
Super Long Line (SLL) Routes
Propagation Limitations
SLR Utilization Considerations
SLR Utilization Example
SLR Crossing for Wide Buses
Designing with HBM Devices
Placement Considerations When Using HBM Devices
Pipelining Considerations for Crossing SLRs
Resource Planning within SLR0
PCIE4C to HBM AXI Paths within SLR0
Configuration
Board Design Tips
Design Creation with RTL
Defining a Good RTL Design Hierarchy
Add I/O Components Near the Top Level
Insert Clocking Elements Near the Top Level
Register Data Paths at Logical Boundaries
Address Floorplanning Considerations
Optimize Hierarchy for Functional and Timing Debug
Apply Attributes at the Module Level
Optimize Hierarchy for Advanced Design Techniques
Example of Upfront Hierarchical Planning for High Speed DSP Designs
Working with Intellectual Property (IP)
Planning IP Requirements
AMBA AXI
Vivado Design Suite IP Catalog
Custom IP
Selecting IP from the IP Catalog
Customizing IP
Using the Customization GUI
Using a Tcl Script
IP Versions and Revision Control
RTL Coding Guidelines
Using Vivado Design Suite HDL Templates
Control Signals and Control Sets
Resets
When and Where to Use a Reset
Synchronous Reset vs. Asynchronous Reset
Reset Coding Example: Multiplier with Synchronous Reset
Reset Coding Example: Multiplier with Asynchronous Reset
Issues When Trying to Eliminate Reset in HDL Code
Clock Enables
Creating Clock Enables
Reset and Clock Enable Precedence
Controlling Enable/Reset Extraction with Synthesis Attributes
Using DIRECT_ENABLE and DIRECT_RESET
Pushing the Logic from the Control Pin to the Data Pin
Tips for Control Signals
Know What You Infer
Inferring RAM and ROM
Performance Considerations When Implementing RAM
Scenarios Preventing Block RAM Output Register Inference
Checking for Multi-Fanout on the Output of Read Data Registers
Checking for Reset Signals on the Address/Read Data Registers
Checking for Feedback Structures in Registers
Mapping Memories to UltraRAM Blocks
Coding for Optimal DSP and Arithmetic Inference
Coding Shift Registers and Delay Lines
Initialization of All Inferred Registers, SRLs, and Memories
Deciding When to Instantiate or Infer
Synthesis Tool Optimization
When Instantiation Is Desirable
Coding Styles to Improve Maximum Frequency
High Fanouts in Critical Paths
Reduce Loads in Portions of the Design That Do Not Require It
Replicate High Fanout Net Drivers
Pipelining Considerations
Consider Pipelining for SSI Devices
Consider Pipelining Up Front
Check Inferred Logic
Determine Whether Pipelining is Needed
Balance Latency
Balance Pipeline Depth and SRL Usage
Avoid Unnecessary Pipelining
Consider Pipelining Macro Primitives
Auto-Pipelining Considerations
Coding Styles to Improve Power
Gate Clock or Data Paths
Maximize Gating Elements
Use Clock Enable Pins of Dedicated Clock Buffers
Use Case Block When Priority Encoder Not Needed
Performance/Power Trade-Off for Block RAMs
Decomposing Deeper Memory Configurations for Balanced Power and Clock Frequency
Running RTL DRCs
Clocking Guidelines
UltraScale Device Clocking
Clock Primitives
Global Clock Buffer Connectivity and Routing Tracks
Clock Routing, Root, and Distribution
Clock Tree Placement and Routing
Clocking Capability
High Fanout Clocks
Low Fanout Clocks
Balanced Utilization of High and Low Fanout Clocks
Clock Constraints
Using LOC Constraints for IO/MMCM/PLL/GT
Using the CLOCK_REGION Property on Clock Buffers
Using a Pblock to Restrict Clock Buffer Placement
Using the USER_CLOCK_ROOT Property on a Clock Net
Using the CLOCK_DELAY_GROUP Constraint on Several Clock Nets
Using the CLOCK_DEDICATED_ROUTE Constraint
Using the CLOCK_LOW_FANOUT Constraint
Clocking Topology Recommendations
Parallel Clock Buffers
Cascaded Clock Buffers
Clock Multiplexing
PLL/MMCM Feedback Path and Compensation Mode
BUFG_GT Divider
SelectIO Clocking
ISERDESE3 and IDDRE1 Clocking
OSERDESE3 Clocking
I/O Timing with MMCM ZHOLD/BUF_IN Compensation
Synchronous CDC
GT Interface Clocking
BUFG_GT with Dynamic Divider
Single Quad vs. Multi-Quad Interface
[RT]XUSRCLK/[RT]XUSRCLK2 Skew Matching
Integrated Block for PCI Express CORECLK/PIPECLK/USERCLK Skew Matching
7 Series Device Clocking
Using Horizontal Clock Region Buffers for Clock Gating
Additional Clocking Considerations for SSI Devices
Clock Skew for Global Clocking Resources in SSI Technology Devices
Designing the Clock Structure
Inference
Synthesis Constraints and Attributes
Use of IP
Instantiation
Controlling the Phase, Frequency, Duty-Cycle, and Jitter of the Clock
Using Clock Modifying Blocks (MMCM and PLL)
Using IDELAYs on Clocks to Control Phase
Using Gated Clocks
Converting Clock Gating to Clock Enable
Gating the Clock Buffer
Controlling and Synchronizing Device Startup
Avoiding Local Clocks
Creating an Output Clock
Clocking Recommendations for Platforms and Dynamic Function eXchange
DFX Behavior for Clock Nets
Reconfigurable Module Internal Clock Nets
Boundary Clock Nets
Clock Domain Crossing
Single-Bit CDC
Multi-Bit CDC
Optimizing for MTBF
Selecting the Correct Value for the DEST_SYNC_FF Parameter
Constraining the Design Correctly
Design Constraints
Organizing the Design Constraints for Compilation
Recommended Constraint Files
Simple Design
Complex Design
Validating the Read Sequence
Recommended Constraints Sequence
Creating Synthesis Constraints
Creating Implementation Constraints
Creating Block-Level Constraints
Specifying Constraints for the Vitis Environment
Defining Timing Constraints
Defining Timing Constraints in Four Steps
Defining Clock Constraints
Identifying Clock Sources
Clock Networks Report
Check Timing Report
Creating Primary Clocks
Input Ports
Gigabit Transceiver Output Pins in 7 Series Devices
Certain Hardware Primitive Output Pins
Creating Generated Clocks
Auto-Derived Clocks
User-Defined Generated Clocks
Path Between Master and Generated Clocks
Verifying Clocks Definition and Coverage
Adjusting Clock Characteristics
Jitter
Additional Uncertainty
Clock Latency at the Source
MMCM or PLL External Feedback Loop Delay
Constraining Input and Output Ports
System Level Perspective
Defining Input Delays
Defining Output Delays
Choosing the Reference Clock
Identifying the Clocks Related to Each Port
Browse the Board Schematics
Browse the Design Schematics
Report Timing from or to the Port
Use Automatically Identified Sampling Clocks
Using a Primary Clock
Using a Virtual Clock
Using a Generated Clock
Rising and Falling Reference Clock Edges
Verifying Delay Constraints
I/O Path Report Command Lines Example
Input to Output Feed-through Path
Example One
Example Two
Using XDC Templates - Source Synchronous Interfaces
Defining Clock Groups and CDC Constraints
Reviewing Clock Interactions
Synchronous
Asynchronous
Exclusive
Categorizing Clock Pairs
Clock Interaction Report
Check Timing Report
Constraining Exclusive Clock Groups
Overlapping Clocks Defined on the Same Clock Source
Overlapping Clocks Driven by a Clock Multiplexer
Constraining Asynchronous Clock Groups and Clock Domain Crossings
Report CDC
Global Constraints Between Clocks in Both Directions
Constraints on Individual CDC Paths
Clock Exceptions Precedence Over set_max_delay
Specifying Timing Exceptions
Timing Exceptions Guidelines
Timing Exceptions Precedence and Priority Rules
Adding False Path Constraints
Use Cases
Impact on Implementation
Impact on Synthesis
Impact on Implementation
Adding Min and Max Delay Constraints
Use Cases
Impact on Synthesis
Impact on Implementation
Avoiding Path Segmentation
Valid Startpoints and Endpoints
Adding Multicycle Path Constraints
Relaxing the Setup Requirement While Keeping Hold Unchanged
Impact on Synthesis and Implementation
Common Mistakes
Other Advanced Timing Constraints
Case Analysis
Disable Timing
Data Check
Max Time Borrow
Defining Power and Thermal Constraints
Defining Physical Constraints
Design Implementation
Running Synthesis
Synthesis Flows
Global Synthesis
Block Design Synthesis
Out-of-Context Synthesis
Incremental Synthesis
Synthesis Optimizations
Synthesis Settings
Synthesis Attributes
KEEP and DONT_TOUCH
MAX_FANOUT
Block-Level Synthesis Strategy
Moving Past Synthesis
Reviewing and Cleaning DRCs
Running Report Methodology
Reviewing the Synthesis Log
Reviewing Timing Constraints
Assessing Post-Synthesis Quality of Results
Following Guidelines to Address Remaining Violations
Dealing with High Levels of Logic
Reviewing Utilization
Reviewing Clock Trees
Clock Buffer Utilization
Clock Tree Topology
Implementing the Design
Using Project Mode vs. Non-Project Mode
Strategies
Directives
Iterative Flows
Analyzing a Design at Different Stages Using Checkpoints
Using Interactive Report Files
Using Incremental Implementation Flows
Automatic Incremental Implementation Mode
Incremental Directives and Target WNS
Configuring the Incremental Flow
Parallel Runs
Compile Time Considerations
Opening the Synthesized Design
Logic Optimization (opt_design)
Optimization Analysis
Placement (place_design)
Placement Analysis
Physical Optimization (phys_opt_design)
Need for Physical Synthesis
Routing (route_design)
Route Analysis
Route Compile Time
Design Closure
Timing Closure
Understanding Timing Closure Criteria
Checking for Valid Constraints
Checking for Positive Timing Slacks
Understanding Timing Reports
Checking That Your Design is Properly Constrained
Fixing Issues Flagged by check_timing
No Clock and Unconstrained Internal Endpoints
Generated Clocks
Loops and Latch Loops
No Input/Output Delays and Partial Input/Output Delays
Multiple Clocks
Fixing Issues Flagged by report_methodology
Methodology DRCs with Impact on Timing Closure
Methodology DRCs with Impact on Signoff Quality and Hardware Stability
Other Timing Methodology DRCs
Assessing the Maximum Frequency of the Design
Baselining the Design
Defining Baseline Constraints
Identifying Which Clocks Must Be Created
Verifying That No Clocks Are Missing
Constraining Clock Domain Crossings
Reviewing Clock Relationships
Identifying Clock Pairs without Common Primary Clocks
Identifying Tight Timing Requirements
Constraining Both Primary and Generated Clocks at the Same Time
Limiting I/O Constraints and Timing Exceptions
Evaluating Design WNS After Each Step
Post-Synthesis and Post-Logic Optimization
Pre- and Post-Placement
Pre- and Post-Physical Optimization
Pre- and Post-Route
Baselining and Timing Constraints Validation Procedure
Analyzing and Resolving Timing Violations
Identifying Timing Violations Root Cause
Reviewing Timing Slack
Using the Design Analysis Report
Analyze Path Characteristics
Review the Logic Level Distribution
Datapath Delay and Logic Levels
Clock Skew and Uncertainty
Reducing Logic Delay
Optimizing Regular Fabric Paths
Optimizing Paths with Dedicated Blocks and Macro Primitives
Reducing Net Delay Caused by Physical Constraints
Reducing Net Delay Caused by Congestion
Congestion Area and Level Definition
Congestion Level Ranges
Interconnect Congestion Level in the Device Window
Congestion in the Placer Log
Congestion in the Router Log
Report Design Analysis Congestion Report
Report Design Analysis Complexity Report
Reducing Clock Skew
Using Intra-Clock Timing Paths
Limiting Synchronous Clock Domain Crossing Paths
Adding Timing Exceptions between Asynchronous Clocks
Applying Common Techniques for Reducing Clock Skew
Applying Techniques for Improving Skew in 7 Series Devices
Improving Skew in UltraScale and UltraScale+ Devices
Reducing Clock Delay in UltraScale and UltraScale+ Devices
Reducing Clock Uncertainty
Using MMCM Settings to Reduce Clock Uncertainty
Using BUFGCE_DIV to Reduce Clock Uncertainty
Applying Common Timing Closure Techniques
Improving the Netlist with Block-Level Synthesis Strategies
Improving Logic Levels
Reducing Control Sets
Follow Control Set Guidelines
Reduce the Number of Control Sets
Optimizing High Fanout Nets
Allow Register Replication
Promote High Fanout Nets to Global Routing
Use Physical Optimization
Prioritize Critical Logic Using the group_path Command
Fixing Large Hold Violations Prior to Routing
Addressing Congestion
Lower Device Utilization
Balance SLR Utilization for SSI Devices
Use Alternate Placer and Router Directives
Turn Off Cross-Boundary Optimization
Reduce MUXF Mapping
Disable LUT Combining
Limit High-Fanout Nets in Congested Areas
Use Cell Bloating
Tuning the Compilation Flow
Using Strategies and Directives
ML Strategies
Predefined Strategies
Custom Strategies
Using Optimization Iterations
Overconstraining the Design
Considering Floorplan
Grouping Critical Logic
Reusing Placement Results
Using Incremental Implementation
Choose a High Quality Reference Checkpoint
Select Incremental Implementation Directives for High Reuse Mode
Avoid Floorplanning and Overconstraining
XPIO-PL Interface Techniques for Timing
SSI Technology Considerations
Using Hard SLR Floorplan Constraints
Using Soft SLR Floorplan Constraints
Using SLR Crossing Registers
Using Auto-Pipelining for SLR Crossings
Clustering Logic
Using Intelligent Design Runs
Power Closure
Estimating Power Throughout the Flow
Using the Power Constraints Advisor
Recommended Power Constraints
Minimum Recommended Constraints
Additional Recommended Constraints
Best Practices for Accurate Power Analysis
Reviewing the Design Power Distribution After Running Power Analysis
Further Refining Control Signal Activity After Running Power Analysis
Power Optimization
Analyzing Your Power Estimation and Optimization Results
Running Power Optimization
Using the Power Optimization Report
Using the Timing Report to Determine the Impact of Power Optimization
Power Timing Slack
Configuration and Debug
Configuration
Debugging
Debugging the PL
Using ILA Cores
Probing the Design
Choosing Debug Nets
Retaining Names of Debug Probe Nets Using MARK_DEBUG
ILA Core and Timing Considerations
ILA Core Designs with High-Speed Clocks
Using VIO Cores
VIO Core Considerations
Debugging Designs in Vivado IP Integrator
Debugging AXI Interfaces in Vivado Hardware Manager
Using In-System IBERT
Running Debug-Related DRCs
Modifying the Implemented Netlist to Replace Existing Debug Probes
Inserting, Deleting, or Editing ILA Cores on an Implemented Netlist
Connecting a Net to a Free External Pin Using Post-Route ECO
Using Remote Debugging
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Vivado Design Suite User and Reference Guides
Vivado Design Suite Tutorials
Other AMD Documentation
Training Resources
Revision History
Please Read: Important Legal Notices

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