The report_design_analysis
command also generates
a Logic Level Distribution table for the worst 1000 paths (default) that you can use to
identify the presence of longer paths in the design. The longest paths are usually
optimized first by the placer to meet timing, which will potentially degrade the
placement quality of shorter paths. You must always try to eliminate the longer paths to
improve the overall timing QoR. For this reason, AMD recommends
reviewing the longest paths before placement.
report_design_analysis -logic_level_distribution -logic_level_dist_paths 5000 -name design_analysis_prePlace
For logic levels above 10, you can use the -min_level
and -max_level
options to provide more distribution information for paths between the min and max level you identify. For example:
report_design_analysis -logic_level_distribution -min_level 16 -max_level 20
-logic_level_dist_paths 5000 -name design_analysis_1
Run the following command to generate the timing report of the longest paths:
report_timing -name longPaths -of_objects [get_timing_paths -setup -to [get_clocks
cpuClk_5] -max_paths 5000 -filter {LOGIC_LEVELS>=16 && LOGIC_LEVELS<=20}]
Based on what you find, you can improve the netlist by changing the RTL or using different synthesis options, or you can modify the timing and physical constraints.