Platforms - 2023.1 English

A platform provides design context to integrate AI Engine design and PL kernels. Platform hardware is represented by an XSA container built using the Vivado Design Suite, and a platform software that includes a board support package (BSP) as well as operating systems, boot files, drivers, libraries, and file systems to link application software and build boot images. The Vitis SDK and PetaLinux tools can be used to build BSPs as well as system and application software customized to your implemented hardware that includes AI Engine and PL kernels.

Types of Platforms

There are two types of hardware platforms, both of which are encapsulated as XSA files built in Vivado. Either type of platform can support Dynamic Function eXchange (DFX) or represent a flat design. In DFX platforms, the AI Engine will reside in the reconfigurable partition that the v++ linker will compile into a reconfigurable module. They share the same connectivity abstractions for CPU control, external memory, streaming I/O, and clocking:

Extensible Platform

An extensible platform contains a pre-synthesized block design into which the Vitis v++ compiler configures the AI Engine hardware. The AI Engine hardware configuration is extracted by the v++ compiler from the libadf.a file that is the result of a compilation of the AI Engine applicable. The v++ compiler also integrates the PL kernels into the platform's hardware design context. The hardware design context provides connectivity abstractions for CPU control, external memory, streaming I/O, and clock networks. When targeting an extensible hardware platform, the AI Engine libadf.a influences the hardware implementation including interfaces between the AI Engine, PL kernels, and platform hardware. For information related to Versal platform clocking, see the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393), and the Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957).

A base platform is an extensible platform provided by AMD that targets an AMD board such as the VCK190, e.g., xilinx_vck190_base_202310_1.xsa (flat) or xilinx_vck190_base_dfx_202310_1.xsa (DFX). For a flat platform, a generated fixed XSA contains the full PL bitstream. Targeting a DFX platform results in two (or more) generated fixed XSAs, one for the static region that is used to boot the device and remains resident and active at runtime, and one (or more) partial XSAs that represent the partial bitstream and metadata associated with the implemented dynamic region.

A custom platform is an extensible XSA that is built using the Vivado Design Suite. Like a base platform, a custom platform is a Vivado hardware design containing a dynamic region block design in which PFM connectivity attributes have been declared. This platform is generated using the write_hw_platform function provided in Vivado. You can build a custom platform starting from a pre-existing Vivado project, from source files provided by AMD for a base platform, or from scratch. For more information, see "Creating Embedded Platforms in Vitis" in the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393) .

Fixed Platform: A fixed hardware platform encapsulates an implemented hardware design built by the v++ linker using the Vivado Design Suite. When targeting a fixed hardware platform, the AI Engine compiler must conform to the AI Engine / PL interface constraints defined by the hardware.

In this chapter, the base platform xilinx_vck190_base_202310_1 is used to show command usage. For targeting the DFX platform xilinx_vck190_base_dfx_202310_1, see Targeting the DFX Platform.

Platform Clocking

Platforms have a variety of clocking: processor, PL, and AI Engine clocking. The following table explains the clocking for each.

Table 1. Platform Clocks
Clock	Description
AI Engine	Can be configured in the platform in the AI Engine IP.
Processor	Can be configured in the platform in the CIPS IP.
Programmable Logic (PL)	Can have multiple clocks and can be configured in the platform.
NoC	Device dependent and can be configured in the platform in the CIPS and NoC IP.
These clocks are derived from the platform and are affected by the device, speed grade, and operating voltage.

For more information related to platform clocking, see Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393). For information on Versal device clocks, see Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957).