The DMA FIFO size and stream switch FIFO size can be viewed in the timeline in Vitis Analyzer using VCD-based analysis. Vitis Analyzer shows the real-time used FIFO depth. From the FIFO depth used, Vitis Analyzer can help analyze design stall issue, optimize FIFO size needed, and then optimize the design performance.
For enabling FIFO size visualization, the VCD dump option of
aiesimulator should be enable. Also, the simulation run
result can be opened in Vitis Analyzer, for
example:aiesimulator --pkg-dir=./Work --online -wdb -ctf
vitis_analyzer aiesimulator_output/default.aierun_summaryFor more options on how to run simulator and open run result in Vitis Analyzer, see AI Engine Stall Analysis in Vitis Analyzer.
Tip: If design hangs in simulation,
use the
--simulation-cycle-timeout=<cycles>
option to stop the aiesimulator simulation at a set
time.