Clocking the PL Kernels - 2023.1 English

PLIO represents an ADF graph interface to a PL component. This component could be a PL kernel, a platform IP representing a signal source or sink, or it could be a data mover to interface the ADF graph to memory. You should provide clock frequency values for these interfaces to ensure simulation results match the results from running the design in hardware.  In addition, when you link the ADF graph into the platform, at the Vitis linker (v++ -link) step, you can direct the tools to generate precisely the clock frequencies required by your application. PL kernels can be independently clocked, and the v++ linker will automatically ensure clock domain crossing circuitry is inserted into the design.

The recommended best practice is as follows:

1. Set the clock frequency of all the PLIO interfaces explicitly in the ADF graph.
2. Provide the same frequency to the Vitis compilation of the attached PL kernel (v++ -c).
3. Provide the same frequency to the Vitis linker (v++ -l) linking the AI Engine graph to the PL kernels and the platform.

See Managing Clock Frequencies in the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393) for more detailed information on how to compile kernels for specific platform clocks and clocking information.