AXI Traffic Generators - 2023.1 English

The AXI Traffic generators are provided as XO files which need to be linked to your simulation platform using the Vitis compiler (v++).  These XO files are called sim_ipc_axis_master_XY.xo and sim_ipc_axis_slave_ZW.xo where XY and ZW correspond to the number of bits in the PLIO interface. For example sim_ipc_axis_master_128.xo provides an AXI4-Stream master data bus that is 128 bits wide. A wider interface allows the PL to achieve the same throughput at a lower clock frequency and allows the AI Engine array to maximize its memory bandwidth. However, the PLIO interface tiles are each 64 bits wide and they are a limited resource. Using one 64-bit PLIO interface at twice the clock speed provides an equivalent bandwidth to a 128-bit PLIO while using only one PLIO tile. This requires the PL to run at twice the clock speed and the optimal choice will vary from application to application.

Two steps are required to use the traffic generators with the Vitis compiler. First, make the connections between the sim_ipc modules and their corresponding AXI4-Stream ports on the AI Engine array. This is typically done in the system.cfg file. Here is an example:

[connectivity]
nk=sim_ipc_axis_master:1:inst_sim_ipc_axis_master
nk=sim_ipc_axis_slave:1:inst_sim_ipc_axis_slave
stream_connect=sim_ipc_axis_master.M00_AXIS:ai_engine_0.DataIn
stream_connect=ai_engine_0.DataOut:sim_ipc_axis_slave.S00_AXIS

nk=sim_ipc_axis_master:<Number Of Masters>:<inst_name_1>.<inst_name_2>.<...>
nk=sim_ipc_axis_slave:<Number Of Slaves>:<inst_name_1>.<inst_name_2>.<...>

v++ -l --platform <platform.xpfm> sim_ipc_axis_master_128.xo sim_ipc_axis_slave_128.xo libadf.a -target hw_emu --config system.cfg

For additional information on how to use XO files with the Vitis compiler see https://github.com/Xilinx/Vitis-Tutorials/tree/master/AI_Engine_Development/Feature_Tutorials/05-AI-engine-versal-integration.