Known Restrictions for Clocking in Versal DFX - 2022.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

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2022.2 English
  • Divided outputs on MBUFGCE primitives are not allowed for boundary clock nets.
    • MBUFG primitives in Versal allows clock division at the leaf level to reduce clock track utilization and improve timing closure on synchronous CDCs. For DFX designs, MBUFG optimization is allowed only for static clock nets, internal RM clock nets, or usage of only the undivided O1 output at the RP boundary; the O1 clock output from a static MBUFG can drive loads in one or more dynamic regions. Boundary clock nets can continue to use BUFGCE_DIV/MMCM/PLL clocking primitives for clock division. However, this will have reduced QoR benefits compared to using MBUFG primitives because latter provides common clock node closer to loads at the leaf level. Hence it is recommended to use MMCM/PLL inside partitions of the DFX design to convert a boundary clock net to internal clock net which can leverage the full set of MBUFG optimizations of Vivado. The CLRB_LEAF input on the MBUFG primitives is used to asynchronously reset the BUFDIV_LEAF dividers. There are cases where special handling is required to ensure that BUFDIV_LEAF dividers are reset to their startup state. If the clock modifying that drives the MBUFG is reset in between the operation, the MBUFG output clocks should also be reset to get synchronized. If divided output clocks from an MBUFG in static drive inputs to Reconfigurable Partitions, the following error will occur:
      ERROR: [DRC HDPR-99] Versal Illegal MBUFGxx drivers in pblock: Reconfigurable Pblock ‘<pblock_name>' contains a MBUFGxx boundary clock net driver ‘<MBUFG Driver Name>'
  • Restrictions in clock resource usage due to clock tile splitting.
    • When a row of clock tiles is shared between multiple RPs, it is possible that some of the sites along this row cannot be used for placement. To avoid potential unroutability because of tile splitting, DFX flow automatically prohibits usage of certain clocking or logical resource tiles. To avoid this scenario, Xilinx recommends keeping at least one clock region wide gap between multiple RP Pblocks if utilization estimation meets the design need.

For example, in a multi-RP design, (with RPs RP1 and RP2), if a clock for RP2 is required to traverse through RP1 to reach loads in RP2, some BRAM sites in the traversed RP (RP1) will be prohibited for use by the placer.

In this scenario some of the clock routing resources in RP1 are also claimed by RP2 so they are shared equally. The RCLK tiles RCLK_BRAM_CLKBUF_* are part of clock routing network and due to sharing by the 2 RPs, only the top or bottom half can be claimed by RP1. Due to the configuration frame programming during reconfiguration, RCLK_BRAM_CLKBUF tiles must be programmed together with all BRAM tiles in the same half column. A Critical Warning will be issued during opt_design for such a scenario. The prohibited sites can be viewed in the Device View.

[Constraints 18-5689] RCLK tile RCLK_BRAM_CLKBUF_CORE_X*Y* is shared by PBLOCK RP1 (owns LSB tracks) and PBLOCK RP2 (owns MSB tracks). For the shared usage, BRAM tiles and their adjacent interface tiles at the NORTH of the shared RCLK tile are prohibited because they could not be used for placement within PBLOCK RP1.