This is the recommended method to
load and link all design sources in the most explicit and thorough manner. The following
steps pull in all necessary design sources and define the RP boundaries.
- Create a new project in memory. While this allows you to select a
target device, the project is not
saved.
create_project -part <part> -in_memory
- Add all the design sources. This can include multiple checkpoints
for static or reconfigurable logic, including lower-level RM
sources.
add_files <top>.dcp add_files <rp1_rmA_top>.dcp add_files <rp1_rmA_lower>.dcp add_files <rp2_rmA_top>.dcp
- Use the
SCOPED_TO_CELLS
property to define relationships between levels of hierarchy.set_property SCOPED_TO_CELLS {<RP1_module_instance>} [get_files <rp1_rmA_top>.dcp] set_property SCOPED_TO_CELLS {<RP1_lower_module_instance>} [get_files <rp1_rmA_lower>.dcp] set_property SCOPED_TO_CELLS {<RP2_module_instance>} [get_files <rp2_rmA_top>.dcp]
- Link the design together, defining all
RPs.
link_design -top <top> -part <part> -reconfig_partitions {<RP1_module_instance> <RP2_module_instance>}
Table 1. link_design Options Command Option Description -part
This is the Xilinx part being targeted (for example, xc7k325tffg900-3
)-top
This is the module/entity name of the module being implemented. This switch can be omitted if set_property top <top_module_name> [current_fileset]
is issued prior tolink_design
.-reconfig_partitions <args>
Specify a list of RPs to load while opening the design. The specified RPs are then marked with the HD.RECONFIGURABLE property for proper handling in the design. -pr_config <arg>
For the project-based design flow only. This option specifies the PR Configuration to apply while opening the design.