Xilinx highly recommends contiguous floorplanning for static regions and reconfigurable Pblocks for the following reasons:
- Disjointed Pblocks in the reconfigurable partition or static region can result in related logic being placed in the disjointed Pblocks, which has a negative impact on timing closure.
- Although static nets can cross over reconfigurable Pblocks to allow communication between two static islands, Xilinx does not recommend this approach, because these locked static nets can block routing during subsequent reconfigurable module implementations.