BLI Floorplan Alignment - 2022.2 English

Vivado Design Suite User Guide: Dynamic Function eXchange (UG909)

Document ID
Release Date
2022.2 English

In Versal, Boundary Logic Interfaces (BLI) tiles are additional register stages available for signals going in and out of Programmable Logic (PL) to and from XPIO logic resources. The BLI register stages helps optimize timing of interface.

Based on the location, a BLI tile can be used by multiple sites.

  • XPHY and XPIOLOGIC sites in XPIO_NIBBLE tile.
  • XPLL sites in CMT_XPLL tile.
  • DPLL sites in CMT_DPLL tile.
  • MMCM sites in CMT_MMCM tile.

Because the BLIs are aligned geometrically exactly to each of these site types that uses it, DFX flow automatically pulls the BLIs based on the tiles in the range of Pblock. Here are some of the rules associated with adding BLI ranges to the reconfigurable Pblock:

  • BLI tiles can be independently added to the reconfigurable Pblock range, even though none of the tiles mentioned above are added in the Pblock range.
  • If an XPIO tile is ranged into an RP, connected BLI will be pulled into the placement footprint.
  • If clocking resources like BUFG, MMCM are ranged in a reconfigurable Pblock, connected BLI will be pulled into the placement footprint by the tool.
  • If AIE_PL or AIE_NOC sites are ranged in a reconfigurable Pblock, connected BLI will be pulled into the RP Pblock range automatically.
  • If a conflict is observed that breaks the automatic pulling of BLI ranges, a DRC is flagged. This can happen when there are two tiles trying to use the same BLI, but those two tiles happen to be in two separate reconfigurable partitions. DRC message also provides the resolution to remove the corresponding tile from the Pblock to avoid the conflict.
Figure 1. BLI Sharing and Floorplan Alignment

In the previous figure, the BLI (red mark) in rp2rm1 has direct connections to the XPIO (marked in green) in rp2rm1, and DDRMC (marked in magenta) in rp1rm1. The yellow highlight shows the nodes of BLI that have direct connections to these tiles. This will trigger the DRC mentioned below because the BLI is being shared by tiles of two different RPs. You can remove one of the shared tiles to resolve the issue reported by the DRC and avoid driving the same BLI by two independent RPs.

HDPR-39: Error BLI tile BLI_CLE_BOT_CORE_1_X78Y0 is owned by both reconfigurable Pblock pblock_rp2rm1 and reconfigurable Pblock pblock_rp1rm1. This is not supported in dynamic function exchange flow. This tile gets pulled in by ranging the tile XPIO_NIBBLE_SC_X78Y0 into reconfigurable Pblock pblock_rp2rm1. To fix the issue, you can adjust the floorplan to remove the tile XPIO_NIBBLE_SC_X78Y0 from reconfigurable Pblock pblock_rp2rm1.

To resolve this, remove the sites of the tile using the following command:

resize_pblock -remove pblock_rp2rm1 [get_sites -of [get_tiles XPIO_NIBBLE_SC_X78Y0]]