As part of improvements to the
Versal
architecture, the smallest unit that can be reconfigured is much smaller than in
previous architectures. The minimum required resources for reconfiguration varies based
on the resource type, and are referred to as a Programmable Unit (PU). Many site types
have improved PU requirement making granularity of reconfigurable Pblocks significantly
improved compared to previous architecture.
Tip: While
the fundamental building blocks are shown in the following images, in real design
scenarios they will be part of a larger collection of resources, creating a
comprehensive floorplan for each dynamic region.
- The following are the details provided for each site type
- Programmable Logic (PL) NoC NMU and NSU: PU is the corresponding NOC_NMU or
NOC_NSU tile.
Figure 1. PL NoC NMU and NSU
- CLE: Two adjacent CLE tiles share a routing resource (interconnect tile). PU is
2 CLE tiles (4 SLICE sites) with shared interconnect.
Figure 2. CLE PU
- BRAM: PU is the corresponding BRAM tile. One BRAM tile includes two RAMB18s and
one RAMB36. Adjacent INTF and INT tiles are automatically pulled into the
routing footprint if it is not covered by the Pblock. Unlike previous
architecture, adjacent CLE sites are not part of BRAM PU.
Figure 3. BRAM PU: RAMB18s and RAMB36 of 1 BRAM
Tile
- URAM: PU is the corresponding URAM tile. One URAM tile includes only 1 URAM
site. Adjacent INTF and INT tiles are automatically pulled into the routing
footprint if it is not covered by the Pblock.
Figure 4. URAM PU: URAM Tile
- DSP: PU is the corresponding DSP tile. One DSP tile includes 2 DSP sites.
Figure 5. DSP PU: DSP Tile
- IRI_QUAD (ODD/EVEN): PU is the corresponding INTF_ROCF_TL_TILE. One tile
includes 4 IRI Quads. INTF at the center of IRI quads is automatically pulled
into routing footprint. Though IRI_QUADs are user range-able, adjacent IRI_QUADs
of RP Pblock are automatically pulled in to the routing footprint because
expanded routing footprint is always 2 INT tile expansion.
Figure 6. Imux Register Interface Quad: PU is INT_ROCF_TL
Tile
-
PCIe 40: PU is the corresponding
PCIEB_BOT_TILE
. Adjacent INTF tiles are automatically included in
the routing footprint of reconfigurable Pblock. Figure 7. PCIe 40 PU is PCIe Tile
- GTY_QUAD: PU is the corresponding GTY_QUAD_SINGLE tile. Sites included in the
tile are GTY_QUAD and GTY_REFCLK. Adjacent INTF_GT tiles are automatically
pulled into the routing footprint of reconfigurable Pblock.
Figure 8. GTY_QUAD PU is GTY_QUAD Tile
- DDRMC and DDRMC_RUI: PUs are corresponding DDRMC_DMC_CORE and DDRMC_RIU_CORE
tiles respectively.
Figure 9. DDMRC PU
Figure 10. DDMRC_RUI PU
- MMCM: PU is corresponding CMT_MMCM tile.
Figure 11. MMCM PU is CMT_MMCM Tile
- XPLL: PU is corresponding CMT_XPLL tile.
Figure 12. XPLL PU is CMT_XPLL Tile
- DPLL: PU is corresponding CMT_DPLL tile.
Figure 13. DPLL PU is CMT_DPLL Tile
- MRMAC: PU is corresponding MRMAC_BOT tile.
Figure 14. MRMAC PU is MRMAC_BOT Tile
- BUFG_FABRIC, BUFG_PS and GCLK_DELAY: These three site types are included in same
tile: CLK_VNOC tile. BUFG_PS will be present only in the VNOC column adjacent to
CIPS. Other VNOC tiles include only BUFG_FABRIC and GCLK_DELAY. PU requirement
is the CLK_VNOC tile.
Figure 15. BUFG_FABRIC, BUFG_PS, and GCLK_DELAY Shares Same Tile
As PU
- XPHY, XPIO and IOB: An IO Bank in Versal
cannot be shared by static and reconfigurable partitions. All XPIO_NIBBLE tiles
of one IO Bank must be used by one partition only.
- BUFG_GT, BUFG_GT_SYNC and GCLK_DELAY: CLK_GT tile is the PU.
Figure 16. BUFG_GT, BUFG_GT_SYNC Share Same PU: CLK_GT
Tile
- XPIPE_QUAD: XPIPE_QUAD tile is the PU.
Figure 17. XPIPE_QUAD PU
- BUFGCE, BUFGCTRL, and BUFGCE_DIV: For the BUFGCE elements in HSR, PU is the
CLK_REBUF_BUFGS_HSR_CORE tile.
Figure 18. Clocking Buffers in HSR Has CLK_REBUF_BUFG_HSR_CORE
Tile As PU
- BUFGCE_HDIO, HDIO_BIAS, HDIO_LOGIC, and IOB: For these sites in HDIO, PU is
HDIO_TILE tile.
Figure 19. Clock Buffers and IOB in HDIO Bank Share Same PU:
HDIO_TILE
See Floorplanning Rules for Clocks Inside an RP for more information.