MMCME3_BASE - 2022.1 English

UltraScale Architecture Libraries Guide (UG974)
Document ID
UG974
Release Date
2022-04-20
Version
2022.1 English

Primitive: Base Mixed Mode Clock Manager (MMCM)

  • PRIMITIVE_GROUP: CLOCK
  • PRIMITIVE_SUBGROUP: PLL
  • Families: UltraScale, UltraScale+

Introduction

The MMCME3 is a mixed signal block designed to support frequency synthesis, clock network deskew, phase adjustment, and jitter reduction. The MMCME3_BASE supports a subset of the more common features and thus is easier to instantiate and use compared to the full features MMCME3_ADV.

Port Descriptions

Port Direction Width Function
Clock Inputs: MMCM input clock.
CLKIN1 Input 1 General clock input.
Clock Outputs: User configurable clock outputs that can be divided versions of the VCO phase outputs (user controllable) from 1 (bypassed) to 128. The output clocks are phase aligned to each other (unless phase shifted) and aligned to the input clock with a proper feedback configuration. The CLKOUT#B outputs are 180 degrees out of phase with the non-B outputs.
CLKOUT0 Output 1 CLKOUT0 output.
CLKOUT0B Output 1 Inverted CLKOUT0 output.
CLKOUT1 Output 1 CLKOUT1 output.
CLKOUT1B Output 1 Inverted CLKOUT1 output.
CLKOUT2 Output 1 CLKOUT2 output.
CLKOUT2B Output 1 Inverted CLKOUT2 output.
CLKOUT3 Output 1 CLKOUT3 output.
CLKOUT3B Output 1 Inverted CLKOUT3 output.
CLKOUT4 Output 1 CLKOUT4 output.
CLKOUT5 Output 1 CLKOUT5 output.
CLKOUT6 Output 1 CLKOUT6 output.
Control Ports: MMCM control ports.
PWRDWN Input 1 Powers down instantiated but unused MMCMs.
RST Input 1 Asynchronous reset signal. The MMCM will synchronously re-enable itself when this signal is released (i.e., MMCM re-enabled). A reset is required when the input clock conditions change (for example, frequency).
Feedback: Required ports to form the feedback path for the MMCM phase alignment capabilities.
CLKFBIN Input 1 Feedback clock pin to the MMCM.
CLKFBOUT Output 1 Dedicated MMCM Feedback clock output.
CLKFBOUTB Output 1 Inverted CLKFBOUT output.
Status Ports: MMCM status ports.
LOCKED Output 1 An output from the MMCM that indicates when the MMCM has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The MMCM automatically locks after power on, no extra reset is required. LOCKED will be deasserted if the input clock stops or the phase alignment is violated (for example, input clock phase shift). The MMCM must be reset after LOCKED is deasserted.

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog Recommended

Available Attributes

Attribute Type Allowed Values Default Description
BANDWIDTH STRING "OPTIMIZED", "HIGH", "LOW" "OPTIMIZED" Specifies the MMCM programming algorithm affecting the jitter, phase margin and other characteristics of the MMCM.
CLKFBOUT_MULT_F 3 significant digit FLOAT 2.000 to 64.000 5.000 Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, will determine the output frequency.
CLKFBOUT_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the MMCM.
CLKIN1_PERIOD FLOAT(nS) 0.000 to 100.000 0.000 Specifies the input period in ns to the MMCM CLKIN1 input. Resolution is down to the ps (3 decimal places). For example, a value of 33.333 would indicate a 30 MHz input clock. This information is mandatory and must be supplied.
CLKOUT0_DIVIDE_F 3 significant digit FLOAT 1.000 to 128.000 1.000 Specifies the amount to divide the associated CLKOUT clock output if a different frequency is desired. This number in combination with the CLKFBOUT_MULT_F and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT4_CASCADE STRING "FALSE", "TRUE" "FALSE" Cascades the output divider (counter) CLKOUT6 into the input of the CLKOUT4 divider for an output clock divider that is greater than 128.
DIVCLK_DIVIDE DECIMAL 1 to 106 1 Specifies the division ratio for all output clocks with respect to the input clock. Effectively divides the CLKIN going into the PFD.
REF_JITTER1 3 significant digit FLOAT 0.000 to 0.999 0.010 Specifies the expected jitter on CLKIN1 to better optimize MMCM performance. A bandwidth setting of OPTIMIZED will attempt to choose the best parameter for input clocking when unknown. If known, then the value provided should be specified in terms of the UI percentage (the maximum peak to peak value) of the expected jitter on the input clock.
STARTUP_WAIT STRING "FALSE", "TRUE" "FALSE" Delays configuration DONE signal from asserting until MMCM is locked.
CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Specifies the duty cycle of the associated CLKOUT output as a decimal number representing the percentage (i.e., 0.50 will generate a 50% duty cycle).
CLKOUT0_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the duty cycle for CLKOUT0.
CLKOUT1_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the duty cycle for CLKOUT1.
CLKOUT2_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the duty cycle for CLKOUT2.
CLKOUT3_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the duty cycle for CLKOUT3.
CLKOUT4_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the duty cycle for CLKOUT4.
CLKOUT5_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the duty cycle for CLKOUT5.
CLKOUT6_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the duty cycle for CLKOUT6.
CLKOUT0_PHASE - CLKOUT6_PHASE: Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the MMCM.
CLKOUT0_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset for CLKOUT0.
CLKOUT1_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset for CLKOUT1.
CLKOUT2_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset for CLKOUT2.
CLKOUT3_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset for CLKOUT3.
CLKOUT4_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset for CLKOUT4.
CLKOUT5_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset for CLKOUT5.
CLKOUT6_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset for CLKOUT6.
CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Specifies the amount to divide the associated CLKOUT clock output if a different frequency is desired. This number in combination with the CLKFBOUT_MULT_F and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT1_DIVIDE DECIMAL 1 to 128 1 Specifies the amount to divide CLKOUT1 to create a different frequency.
CLKOUT2_DIVIDE DECIMAL 1 to 128 1 Specifies the amount to divide CLKOUT2 to create a different frequency.
CLKOUT3_DIVIDE DECIMAL 1 to 128 1 Specifies the amount to divide CLKOUT3 to create a different frequency.
CLKOUT4_DIVIDE DECIMAL 1 to 128 1 Specifies the amount to divide CLKOUT4 to create a different frequency.
CLKOUT5_DIVIDE DECIMAL 1 to 128 1 Specifies the amount to divide CLKOUT5 to create a different frequency.
CLKOUT6_DIVIDE DECIMAL 1 to 128 1 Specifies the amount to divide CLKOUT6 to create a different frequency.
Programmable Inversion Attributes: Specifies whether or not to use the optional inversions on specific pins of this component to change the active polarity of the pin function. When set to 1 on a clock input pin (CLKIN1 or CLKFBIN), the phase is effectively shifted 180 degrees. When set to 1 on other pins, it changes the function to behave active-Low rather than active-High. If an external inverter is specified on one of these associated pins, the Vivado Design Suite will automatically set this attribute during the opt_design stage so that additional logic is not necessary for changing the input polarity.
IS_CLKFBIN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKFBIN pin.
IS_CLKIN1_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKIN1 pin.
IS_PWRDWN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the PWRDWN pin.
IS_RST_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the RST pin.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- MMCME3_BASE: Base Mixed Mode Clock Manager (MMCM)
--              UltraScale
-- Xilinx HDL Language Template, version 2022.1

MMCME3_BASE_inst : MMCME3_BASE
generic map (
   BANDWIDTH => "OPTIMIZED",   -- Jitter programming (HIGH, LOW, OPTIMIZED)
   CLKFBOUT_MULT_F => 5.0,     -- Multiply value for all CLKOUT (2.000-64.000)
   CLKFBOUT_PHASE => 0.0,      -- Phase offset in degrees of CLKFB (-360.000-360.000)
   CLKIN1_PERIOD => 0.0,       -- Input clock period in ns units, ps resolution (i.e., 33.333 is 30 MHz).
   CLKOUT0_DIVIDE_F => 1.0,    -- Divide amount for CLKOUT0 (1.000-128.000)
   -- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
   CLKOUT0_DUTY_CYCLE => 0.5,
   CLKOUT1_DUTY_CYCLE => 0.5,
   CLKOUT2_DUTY_CYCLE => 0.5,
   CLKOUT3_DUTY_CYCLE => 0.5,
   CLKOUT4_DUTY_CYCLE => 0.5,
   CLKOUT5_DUTY_CYCLE => 0.5,
   CLKOUT6_DUTY_CYCLE => 0.5,
   -- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
   CLKOUT0_PHASE => 0.0,
   CLKOUT1_PHASE => 0.0,
   CLKOUT2_PHASE => 0.0,
   CLKOUT3_PHASE => 0.0,
   CLKOUT4_PHASE => 0.0,
   CLKOUT5_PHASE => 0.0,
   CLKOUT6_PHASE => 0.0,
   -- CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
   CLKOUT1_DIVIDE => 1,
   CLKOUT2_DIVIDE => 1,
   CLKOUT3_DIVIDE => 1,
   CLKOUT4_DIVIDE => 1,
   CLKOUT5_DIVIDE => 1,
   CLKOUT6_DIVIDE => 1,
   CLKOUT4_CASCADE => "FALSE", -- Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
   DIVCLK_DIVIDE => 1,         -- Master division value (1-106)
   -- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
   IS_CLKFBIN_INVERTED => '0', -- Optional inversion for CLKFBIN
   IS_CLKIN1_INVERTED => '0',  -- Optional inversion for CLKIN1
   IS_PWRDWN_INVERTED => '0',  -- Optional inversion for PWRDWN
   IS_RST_INVERTED => '0',     -- Optional inversion for RST
   REF_JITTER1 => 0.0,         -- Reference input jitter in UI (0.000-0.999)
   STARTUP_WAIT => "FALSE"     -- Delays DONE until MMCM is locked (FALSE, TRUE)
)
port map (
   -- Clock Outputs outputs: User configurable clock outputs
   CLKOUT0 => CLKOUT0,     -- 1-bit output: CLKOUT0
   CLKOUT0B => CLKOUT0B,   -- 1-bit output: Inverted CLKOUT0
   CLKOUT1 => CLKOUT1,     -- 1-bit output: CLKOUT1
   CLKOUT1B => CLKOUT1B,   -- 1-bit output: Inverted CLKOUT1
   CLKOUT2 => CLKOUT2,     -- 1-bit output: CLKOUT2
   CLKOUT2B => CLKOUT2B,   -- 1-bit output: Inverted CLKOUT2
   CLKOUT3 => CLKOUT3,     -- 1-bit output: CLKOUT3
   CLKOUT3B => CLKOUT3B,   -- 1-bit output: Inverted CLKOUT3
   CLKOUT4 => CLKOUT4,     -- 1-bit output: CLKOUT4
   CLKOUT5 => CLKOUT5,     -- 1-bit output: CLKOUT5
   CLKOUT6 => CLKOUT6,     -- 1-bit output: CLKOUT6
   -- Feedback outputs: Clock feedback ports
   CLKFBOUT => CLKFBOUT,   -- 1-bit output: Feedback clock
   CLKFBOUTB => CLKFBOUTB, -- 1-bit output: Inverted CLKFBOUT
   -- Status Ports outputs: MMCM status ports
   LOCKED => LOCKED,       -- 1-bit output: LOCK
   -- Clock Inputs inputs: Clock input
   CLKIN1 => CLKIN1,       -- 1-bit input: Clock
   -- Control Ports inputs: MMCM control ports
   PWRDWN => PWRDWN,       -- 1-bit input: Power-down
   RST => RST,             -- 1-bit input: Reset
   -- Feedback inputs: Clock feedback ports
   CLKFBIN => CLKFBIN      -- 1-bit input: Feedback clock
);

-- End of MMCME3_BASE_inst instantiation

Verilog Instantiation Template


// MMCME3_BASE: Base Mixed Mode Clock Manager (MMCM)
//              UltraScale
// Xilinx HDL Language Template, version 2022.1

MMCME3_BASE #(
   .BANDWIDTH("OPTIMIZED"),    // Jitter programming (HIGH, LOW, OPTIMIZED)
   .CLKFBOUT_MULT_F(5.0),      // Multiply value for all CLKOUT (2.000-64.000)
   .CLKFBOUT_PHASE(0.0),       // Phase offset in degrees of CLKFB (-360.000-360.000)
   .CLKIN1_PERIOD(0.0),        // Input clock period in ns units, ps resolution (i.e., 33.333 is 30 MHz).
   .CLKOUT0_DIVIDE_F(1.0),     // Divide amount for CLKOUT0 (1.000-128.000)
   // CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
   .CLKOUT0_DUTY_CYCLE(0.5),
   .CLKOUT1_DUTY_CYCLE(0.5),
   .CLKOUT2_DUTY_CYCLE(0.5),
   .CLKOUT3_DUTY_CYCLE(0.5),
   .CLKOUT4_DUTY_CYCLE(0.5),
   .CLKOUT5_DUTY_CYCLE(0.5),
   .CLKOUT6_DUTY_CYCLE(0.5),
   // CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
   .CLKOUT0_PHASE(0.0),
   .CLKOUT1_PHASE(0.0),
   .CLKOUT2_PHASE(0.0),
   .CLKOUT3_PHASE(0.0),
   .CLKOUT4_PHASE(0.0),
   .CLKOUT5_PHASE(0.0),
   .CLKOUT6_PHASE(0.0),
   // CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
   .CLKOUT1_DIVIDE(1),
   .CLKOUT2_DIVIDE(1),
   .CLKOUT3_DIVIDE(1),
   .CLKOUT4_DIVIDE(1),
   .CLKOUT5_DIVIDE(1),
   .CLKOUT6_DIVIDE(1),
   .CLKOUT4_CASCADE("FALSE"),  // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE)
   .DIVCLK_DIVIDE(1),          // Master division value (1-106)
   // Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
   .IS_CLKFBIN_INVERTED(1'b0), // Optional inversion for CLKFBIN
   .IS_CLKIN1_INVERTED(1'b0),  // Optional inversion for CLKIN1
   .IS_PWRDWN_INVERTED(1'b0),  // Optional inversion for PWRDWN
   .IS_RST_INVERTED(1'b0),     // Optional inversion for RST
   .REF_JITTER1(0.0),          // Reference input jitter in UI (0.000-0.999)
   .STARTUP_WAIT("FALSE")      // Delays DONE until MMCM is locked (FALSE, TRUE)
)
MMCME3_BASE_inst (
   // Clock Outputs outputs: User configurable clock outputs
   .CLKOUT0(CLKOUT0),     // 1-bit output: CLKOUT0
   .CLKOUT0B(CLKOUT0B),   // 1-bit output: Inverted CLKOUT0
   .CLKOUT1(CLKOUT1),     // 1-bit output: CLKOUT1
   .CLKOUT1B(CLKOUT1B),   // 1-bit output: Inverted CLKOUT1
   .CLKOUT2(CLKOUT2),     // 1-bit output: CLKOUT2
   .CLKOUT2B(CLKOUT2B),   // 1-bit output: Inverted CLKOUT2
   .CLKOUT3(CLKOUT3),     // 1-bit output: CLKOUT3
   .CLKOUT3B(CLKOUT3B),   // 1-bit output: Inverted CLKOUT3
   .CLKOUT4(CLKOUT4),     // 1-bit output: CLKOUT4
   .CLKOUT5(CLKOUT5),     // 1-bit output: CLKOUT5
   .CLKOUT6(CLKOUT6),     // 1-bit output: CLKOUT6
   // Feedback outputs: Clock feedback ports
   .CLKFBOUT(CLKFBOUT),   // 1-bit output: Feedback clock
   .CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT
   // Status Ports outputs: MMCM status ports
   .LOCKED(LOCKED),       // 1-bit output: LOCK
   // Clock Inputs inputs: Clock input
   .CLKIN1(CLKIN1),       // 1-bit input: Clock
   // Control Ports inputs: MMCM control ports
   .PWRDWN(PWRDWN),       // 1-bit input: Power-down
   .RST(RST),             // 1-bit input: Reset
   // Feedback inputs: Clock feedback ports
   .CLKFBIN(CLKFBIN)      // 1-bit input: Feedback clock
);

// End of MMCME3_BASE_inst instantiation

Related Information

  • See the UltraScale Architecture Clocking Resources User Guide (UG572).