Primitive: Base Mixed Mode Clock Manager (MMCM)
- PRIMITIVE_GROUP: CLOCK
- PRIMITIVE_SUBGROUP: PLL
- Families: UltraScale+
Introduction
The MMCME4 is a mixed signal block designed to support frequency synthesis, clock network deskew, phase adjustment and jitter reduction. The MMCME4_BASE supports a subset of the more common features and thus is easier to instantiate and use compared to the full features MMCME4_ADV.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| CLKFBIN | Input | 1 | Feedback clock pin to the MMCM. |
| CLKFBOUT | Output | 1 | Dedicated MMCM Feedback clock output. |
| CLKFBOUTB | Output | 1 | Inverted CLKFBOUT. |
| CLKIN1 | Input | 1 | Primary clock input. |
| CLKOUT0 | Output | 1 | CLKOUT0 output. |
| CLKOUT0B | Output | 1 | Inverted CLKOUT0. |
| CLKOUT1 | Output | 1 | CLKOUT1 output. |
| CLKOUT1B | Output | 1 | Inverted CLKOUT1. |
| CLKOUT2 | Output | 1 | CLKOUT2 output. |
| CLKOUT2B | Output | 1 | Inverted CLKOUT2. |
| CLKOUT3 | Output | 1 | CLKOUT3 output. |
| CLKOUT3B | Output | 1 | Inverted CLKOUT3. |
| CLKOUT4 | Output | 1 | CLKOUT4 output. |
| CLKOUT5 | Output | 1 | CLKOUT5 output. |
| CLKOUT6 | Output | 1 | CLKOUT6 output. |
| LOCKED | Output | 1 | An output from the MMCM that indicates when the MMCM has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The MMCM automatically locks after power on, no extra reset is required. LOCKED will be deasserted if the input clock stops or the phase alignment is violated (for example, input clock phase shift). The MMCM must be reset after LOCKED is deasserted. |
| PWRDWN | Input | 1 | Powers down MMCM components, thus reducing power consumption when derived clocks are not in use for sustained periods of time. Upon release of PWRDWN, the MMCM must regain LOCK before use. |
| RST | Input | 1 | Asynchronous reset signal. The MMCM will synchronously re-enable itself when this signal is released (i.e., MMCM re-enabled). A reset is required when the input clock conditions change (for example, frequency). |
Design Entry Method
| Instantiation | Yes |
| Inference | No |
| IP and IP Integrator Catalog | Recommended |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| BANDWIDTH | STRING | "OPTIMIZED", "HIGH", "LOW" | "OPTIMIZED" | Specifies the MMCM programming algorithm affecting the jitter, phase margin and other characteristics of the MMCM. |
| CLKFBOUT_MULT_F | 3 significant digit FLOAT | 2.000 to 128.000 | 5.000 | Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, will determine the output frequency. |
| CLKFBOUT_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the MMCM. |
| CLKIN1_PERIOD | FLOAT(nS) | 0.000 to 100.000 | 0.000 | Specifies the input period to the CLKIN1 in ns. |
| CLKOUT0_DIVIDE_F | 3 significant digit FLOAT | 1.000 to 128.000 | 1.000 | Specifies the amount to fractional divide the associated CLKOUT clock output if a different frequency is desired. This number in combination with the CLKFBOUT_MULT_F and DIVCLK_DIVIDE values will determine the output frequency. |
| CLKOUT0_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the Duty Cycle of CLKOUT0 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle). |
| CLKOUT0_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset in degrees of the CLKOUT0 output. |
| CLKOUT1_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount by which to divide CLKOUT1 to create a different frequency. |
| CLKOUT1_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT1. |
| CLKOUT1_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT1. |
| CLKOUT2_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount to divide CLKOUT2 to create a different frequency. |
| CLKOUT2_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT2. |
| CLKOUT2_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT2 |
| CLKOUT3_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount to divide CLKOUT3 to create a different frequency. |
| CLKOUT3_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT3. |
| CLKOUT3_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT3. |
| CLKOUT4_CASCADE | STRING | "FALSE", "TRUE" | "FALSE" | Cascades the output divider (counter) CLKOUT6 into the input of the CLKOUT4 divider for an output clock divider that is greater than 128, effectively providing a total divide value of 16,384. |
| CLKOUT4_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount by which to divide CLKOUT4 to create a different frequency. |
| CLKOUT4_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT4. |
| CLKOUT4_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT4. |
| CLKOUT5_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount by which to divide CLKOUT5 to create a different frequency. |
| CLKOUT5_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT5. |
| CLKOUT5_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT5. |
| CLKOUT6_DIVIDE | DECIMAL | 1 to 128 | 1 | Specifies the amount by which to divide CLKOUT6 to create a different frequency. |
| CLKOUT6_DUTY_CYCLE | 3 significant digit FLOAT | 0.001 to 0.999 | 0.500 | Specifies the duty cycle for CLKOUT6. |
| CLKOUT6_PHASE | 3 significant digit FLOAT | -360.000 to 360.000 | 0.000 | Specifies the phase offset for CLKOUT6. |
| DIVCLK_DIVIDE | DECIMAL | 1 to 106 | 1 | Specifies the division ratio for all output clocks with respect to the input clock. Effectively divides the CLKIN going into the PFD. |
| IS_CLKFBIN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKFBIN pin. |
| IS_CLKIN1_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLKIN1 pin. |
| IS_PWRDWN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the PWRDWN pin. |
| IS_RST_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RST pin. |
| REF_JITTER1 | 3 significant digit FLOAT | 0.000 to 0.999 | 0.010 | Specifies the expected jitter on the CLKIN1. |
| STARTUP_WAIT | STRING | "FALSE", "TRUE" | "FALSE" | Delays configuration DONE signal from asserting until MMCM is locked. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- MMCME4_BASE: Base Mixed Mode Clock Manager (MMCM)
-- UltraScale
-- Xilinx HDL Language Template, version 2022.1
MMCME4_BASE_inst : MMCME4_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- Jitter programming
CLKFBOUT_MULT_F => 5.0, -- Multiply value for all CLKOUT
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB
CLKIN1_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
CLKOUT0_DIVIDE_F => 1.0, -- Divide amount for CLKOUT0
CLKOUT0_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT0
CLKOUT0_PHASE => 0.0, -- Phase offset for CLKOUT0
CLKOUT1_DIVIDE => 1, -- Divide amount for CLKOUT (1-128)
CLKOUT1_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT1_PHASE => 0.0, -- Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT2_DIVIDE => 1, -- Divide amount for CLKOUT (1-128)
CLKOUT2_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT2_PHASE => 0.0, -- Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT3_DIVIDE => 1, -- Divide amount for CLKOUT (1-128)
CLKOUT3_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT3_PHASE => 0.0, -- Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT4_CASCADE => "FALSE", -- Divide amount for CLKOUT (1-128)
CLKOUT4_DIVIDE => 1, -- Divide amount for CLKOUT (1-128)
CLKOUT4_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT4_PHASE => 0.0, -- Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT5_DIVIDE => 1, -- Divide amount for CLKOUT (1-128)
CLKOUT5_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT5_PHASE => 0.0, -- Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT6_DIVIDE => 1, -- Divide amount for CLKOUT (1-128)
CLKOUT6_DUTY_CYCLE => 0.5, -- Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT6_PHASE => 0.0, -- Phase offset for CLKOUT outputs (-360.000-360.000).
DIVCLK_DIVIDE => 1, -- Master division value
IS_CLKFBIN_INVERTED => '0', -- Optional inversion for CLKFBIN
IS_CLKIN1_INVERTED => '0', -- Optional inversion for CLKIN1
IS_PWRDWN_INVERTED => '0', -- Optional inversion for PWRDWN
IS_RST_INVERTED => '0', -- Optional inversion for RST
REF_JITTER1 => 0.0, -- Reference input jitter in UI (0.000-0.999).
STARTUP_WAIT => "FALSE" -- Delays DONE until MMCM is locked
)
port map (
CLKFBOUT => CLKFBOUT, -- 1-bit output: Feedback clock pin to the MMCM
CLKFBOUTB => CLKFBOUTB, -- 1-bit output: Inverted CLKFBOUT
CLKOUT0 => CLKOUT0, -- 1-bit output: CLKOUT0
CLKOUT0B => CLKOUT0B, -- 1-bit output: Inverted CLKOUT0
CLKOUT1 => CLKOUT1, -- 1-bit output: CLKOUT1
CLKOUT1B => CLKOUT1B, -- 1-bit output: Inverted CLKOUT1
CLKOUT2 => CLKOUT2, -- 1-bit output: CLKOUT2
CLKOUT2B => CLKOUT2B, -- 1-bit output: Inverted CLKOUT2
CLKOUT3 => CLKOUT3, -- 1-bit output: CLKOUT3
CLKOUT3B => CLKOUT3B, -- 1-bit output: Inverted CLKOUT3
CLKOUT4 => CLKOUT4, -- 1-bit output: CLKOUT4
CLKOUT5 => CLKOUT5, -- 1-bit output: CLKOUT5
CLKOUT6 => CLKOUT6, -- 1-bit output: CLKOUT6
LOCKED => LOCKED, -- 1-bit output: LOCK
CLKFBIN => CLKFBIN, -- 1-bit input: Feedback clock pin to the MMCM
CLKIN1 => CLKIN1, -- 1-bit input: Primary clock
PWRDWN => PWRDWN, -- 1-bit input: Power-down
RST => RST -- 1-bit input: Reset
);
-- End of MMCME4_BASE_inst instantiation
Verilog Instantiation Template
// MMCME4_BASE: Base Mixed Mode Clock Manager (MMCM)
// UltraScale
// Xilinx HDL Language Template, version 2022.1
MMCME4_BASE #(
.BANDWIDTH("OPTIMIZED"), // Jitter programming
.CLKFBOUT_MULT_F(5.0), // Multiply value for all CLKOUT
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB
.CLKIN1_PERIOD(0.0), // Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
.CLKOUT0_DIVIDE_F(1.0), // Divide amount for CLKOUT0
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0
.CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0
.CLKOUT1_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT1_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT2_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT2_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT3_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT3_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT4_CASCADE("FALSE"), // Divide amount for CLKOUT (1-128)
.CLKOUT4_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT4_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT5_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT5_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT5_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.CLKOUT6_DIVIDE(1), // Divide amount for CLKOUT (1-128)
.CLKOUT6_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT outputs (0.001-0.999).
.CLKOUT6_PHASE(0.0), // Phase offset for CLKOUT outputs (-360.000-360.000).
.DIVCLK_DIVIDE(1), // Master division value
.IS_CLKFBIN_INVERTED(1'b0), // Optional inversion for CLKFBIN
.IS_CLKIN1_INVERTED(1'b0), // Optional inversion for CLKIN1
.IS_PWRDWN_INVERTED(1'b0), // Optional inversion for PWRDWN
.IS_RST_INVERTED(1'b0), // Optional inversion for RST
.REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delays DONE until MMCM is locked
)
MMCME4_BASE_inst (
.CLKFBOUT(CLKFBOUT), // 1-bit output: Feedback clock pin to the MMCM
.CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT
.CLKOUT0(CLKOUT0), // 1-bit output: CLKOUT0
.CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0
.CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1
.CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1
.CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2
.CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2
.CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3
.CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3
.CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4
.CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5
.CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6
.LOCKED(LOCKED), // 1-bit output: LOCK
.CLKFBIN(CLKFBIN), // 1-bit input: Feedback clock pin to the MMCM
.CLKIN1(CLKIN1), // 1-bit input: Primary clock
.PWRDWN(PWRDWN), // 1-bit input: Power-down
.RST(RST) // 1-bit input: Reset
);
// End of MMCME4_BASE_inst instantiation
Related Information
- See the UltraScale Architecture Clocking Resources User Guide (UG572).