RIU_OR - 2022.1 English

Primitive: Register Interface Unit Selection Block

PRIMITIVE_GROUP: I/O
PRIMITIVE_SUBGROUP: BITSLICE
Families: UltraScale, UltraScale+

Introduction

The RIU_OR controls the Register Interface Unit selection between the lower and upper nibble BITSLICE_CONTROL within a BYTE.

Port Descriptions

Port	Direction	Width	Function
RIU_RD_DATA<15:0>	Output	16	RIU data bus to the controller.
RIU_RD_DATA_LOW<15:0>	Input	16	RIU data bus from the controller to the lower nibble BITSLICE_CONTROL.
RIU_RD_DATA_UPP<15:0>	Input	16	RIU data bus from the controller to the upper nibble BITSLICE_CONTROL.
RIU_RD_VALID	Output	1	Combined RIU read valid signal to the controller.
RIU_RD_VALID_LOW	Input	1	RIU_VALID of the lower nibble BITSLICE_CONTROL.
RIU_RD_VALID_UPP	Input	1	RIU_VALID of the upper nibble BITSLICE_CONTROL.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	Yes

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- RIU_OR: Register Interface Unit Selection Block
--         UltraScale
-- Xilinx HDL Language Template, version 2022.1

RIU_OR_inst : RIU_OR
generic map (
   SIM_DEVICE => "ULTRASCALE_PLUS"  -- Set the device version for simulation functionality (ULTRASCALE,
                                    -- ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
)
port map (
   RIU_RD_DATA => RIU_RD_DATA,           -- 16-bit output: RIU data bus to the controller
   RIU_RD_VALID => RIU_RD_VALID,         -- 1-bit output: Combined RIU read valid signal to the controller
   RIU_RD_DATA_LOW => RIU_RD_DATA_LOW,   -- 16-bit input: RIU data bus from the controller to the lower
                                         -- nibble BITSLICE_CONTROL

   RIU_RD_DATA_UPP => RIU_RD_DATA_UPP,   -- 16-bit input: RIU data bus from the controller to the upper
                                         -- nibble BITSLICE_CONTROL

   RIU_RD_VALID_LOW => RIU_RD_VALID_LOW, -- 1-bit input: RIU_VALID of the lower nibble BITSLICE_CONTROL
   RIU_RD_VALID_UPP => RIU_RD_VALID_UPP  -- 1-bit input: RIU_VALID of the upper nibble BITSLICE_CONTROL
);

-- End of RIU_OR_inst instantiation

Verilog Instantiation Template


// RIU_OR: Register Interface Unit Selection Block
//         UltraScale
// Xilinx HDL Language Template, version 2022.1

RIU_OR #(
   .SIM_DEVICE("ULTRASCALE_PLUS")  // Set the device version for simulation functionality (ULTRASCALE,
                                   // ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
)
RIU_OR_inst (
   .RIU_RD_DATA(RIU_RD_DATA),           // 16-bit output: RIU data bus to the controller
   .RIU_RD_VALID(RIU_RD_VALID),         // 1-bit output: Combined RIU read valid signal to the controller
   .RIU_RD_DATA_LOW(RIU_RD_DATA_LOW),   // 16-bit input: RIU data bus from the controller to the lower
                                        // nibble BITSLICE_CONTROL

   .RIU_RD_DATA_UPP(RIU_RD_DATA_UPP),   // 16-bit input: RIU data bus from the controller to the upper
                                        // nibble BITSLICE_CONTROL

   .RIU_RD_VALID_LOW(RIU_RD_VALID_LOW), // 1-bit input: RIU_VALID of the lower nibble BITSLICE_CONTROL
   .RIU_RD_VALID_UPP(RIU_RD_VALID_UPP)  // 1-bit input: RIU_VALID of the upper nibble BITSLICE_CONTROL
);

// End of RIU_OR_inst instantiation

Related Information

See the UltraScale Architecture SelectIO Resources User Guide (UG571).