PLLE4_BASE - 2022.1 English

UltraScale Architecture Libraries Guide (UG974)
Document ID
UG974
Release Date
2022-04-20
Version
2022.1 English

Primitive: Base Phase-Locked Loop (PLL)

  • PRIMITIVE_GROUP: CLOCK
  • PRIMITIVE_SUBGROUP: PLL
  • Families: UltraScale+
Page-1 Sheet.1 PLLE4_BASE PLLE4_BASE Text Line.88 CLKOUT1B CLKOUT1B Text Line.93 CLKOUT1 CLKOUT1 Text Line.36 LOCKED LOCKED Text Line.39 PWRDWN PWRDWN Sheet.6 RST RST Text Line.6 CLKOUTPHYEN CLKOUTPHYEN Text Line.7 CLKIN CLKIN Text Line.8 CLKFBIN CLKFBIN Text Line.9 CLKOUT0 CLKOUT0 Text Line.10 CLKOUTPHY CLKOUTPHY Text Line.12 CLKFBOUT CLKFBOUT Text Line.11 CLKOUT0B CLKOUT0B D Flip-Flop.12 D Flip-Flop.23 Sheet.16 X15111-102615 Sheet.17 Sheet.18 Sheet.19 X15111-061319

Introduction

The PLLE4 is used for high-speed I/O clocking using Bitslice components as well as general clocking requirements. In general, the PLLE4 has less jitter and reduced power characteristics compared to the MMCME4 which makes it preferable for clocking behaviors that do not require features only available to the MMCME4.

Port Descriptions

Port Direction Width Function
CLKFBIN Input 1 Feedback clock pin to the PLL.
CLKFBOUT Output 1 Dedicated PLL Feedback clock output.
CLKIN Input 1 Input clock.
CLKOUTPHY Output 1 General clock output connected to I/O Bitslice components.
CLKOUTPHYEN Input 1 Enable signal for CLKOUTPHY.
CLKOUT0 Output 1 General clock output CLKOUT0. Generally connected to a global buffer.
CLKOUT0B Output 1 Inverted CLKOUT0.
CLKOUT1 Output 1 General clock output CLKOUT1.
CLKOUT1B Output 1 Inverted CLKOUT1.
LOCKED Output 1 An output from the PLL that indicates when the PLL has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The PLL automatically locks after power on, no extra reset is required. LOCKED will be deasserted if the input clock stops or the phase alignment is violated (for example, input clock phase shift). The PLL must be reset after LOCKED is deasserted.
PWRDWN Input 1 Powers down instantiated but unused PLLs.
RST Input 1 The RST signal is an asynchronous reset for the PLL. The PLL will synchronously re-enable itself when this signal is released and go through a new phase alignment and lock cycle. A reset is required when the input clock conditions change (for example, frequency).

Design Entry Method

Instantiation Yes
Inference No
IP and IP Integrator Catalog Recommended

Available Attributes

Attribute Type Allowed Values Default Description
CLKFBOUT_MULT DECIMAL 2 to 21 5 Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number, in combination with the associated CLKOUT#_DIVIDE value and DIVCLK_DIVIDE value, will determine the output frequency.
CLKFBOUT_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the clock feedback output. Shifting the feedback clock results in a negative phase shift of all output clocks to the PLL.
CLKIN_PERIOD FLOAT(nS) 0.000 to 14.286 0.000 Specifies the input period in ns to the PLL CLKIN input. Resolution is down to the ps (3 decimal places). For example a value of 33.333 would indicate a 30 MHz input clock. This information is mandatory and must be supplied.
CLKOUTPHY_MODE STRING "VCO_2X", "VCO", "VCO_HALF" "VCO_2X" Specifies the frequency of the CLKOUTPHY clock output.
CLKOUT0_DIVIDE DECIMAL 1 to 128 1 Specifies the amount to divide the CLKOUT0 output. This number, in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values, will determine the output frequency.
CLKOUT0_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT0 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle).
CLKOUT0_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT0 output.
CLKOUT1_DIVIDE DECIMAL 1 to 128 1 Specifies the amount to divide the CLKOUT1 output. This number in combination with the CLKFBOUT_MULT and DIVCLK_DIVIDE values will determine the output frequency.
CLKOUT1_DUTY_CYCLE 3 significant digit FLOAT 0.001 to 0.999 0.500 Specifies the Duty Cycle of CLKOUT1 clock output in percentage (i.e., 0.500 will generate a 50% duty cycle).
CLKOUT1_PHASE 3 significant digit FLOAT -360.000 to 360.000 0.000 Specifies the phase offset in degrees of the CLKOUT1 output.
DIVCLK_DIVIDE DECIMAL 1 to 15 1 Specifies the division ratio for all output clocks with respect to the input clock. Effectively divides the CLKIN going into the PFD.
IS_CLKFBIN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKFBIN pin of this component.
IS_CLKIN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the CLKIN pin of this component.
IS_PWRDWN_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the PWRDWN pin of this component.
IS_RST_INVERTED BINARY 1'b0 to 1'b1 1'b0 Specifies whether or not to use the optional inversion on the RST pin of this component.
REF_JITTER 3 significant digit FLOAT 0.000 to 0.999 0.010 Allows specification of the expected jitter on CLKIN to better optimize PLL performance. When unknown, a bandwidth setting of OPTIMIZED will attempt to choose the best parameter for input clocking. If known, then the value provided should be specified in terms of the UI percentage (the maximum peak to peak value) of the expected jitter on the input clock.
STARTUP_WAIT STRING "FALSE", "TRUE" "FALSE" Delays configuration DONE signal from asserting until PLL is locked.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- PLLE4_BASE: Base Phase-Locked Loop (PLL)
--             UltraScale
-- Xilinx HDL Language Template, version 2022.1

PLLE4_BASE_inst : PLLE4_BASE
generic map (
   CLKFBOUT_MULT => 5,         -- Multiply value for all CLKOUT
   CLKFBOUT_PHASE => 0.0,      -- Phase offset in degrees of CLKFB
   CLKIN_PERIOD => 0.0,        -- Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
   CLKOUT0_DIVIDE => 1,        -- Divide amount for CLKOUT0
   CLKOUT0_DUTY_CYCLE => 0.5,  -- Duty cycle for CLKOUT0
   CLKOUT0_PHASE => 0.0,       -- Phase offset for CLKOUT0
   CLKOUT1_DIVIDE => 1,        -- Divide amount for CLKOUT1
   CLKOUT1_DUTY_CYCLE => 0.5,  -- Duty cycle for CLKOUT1
   CLKOUT1_PHASE => 0.0,       -- Phase offset for CLKOUT1
   CLKOUTPHY_MODE => "VCO_2X", -- Frequency of the CLKOUTPHY
   DIVCLK_DIVIDE => 1,         -- Master division value
   IS_CLKFBIN_INVERTED => '0', -- Optional inversion for CLKFBIN
   IS_CLKIN_INVERTED => '0',   -- Optional inversion for CLKIN
   IS_PWRDWN_INVERTED => '0',  -- Optional inversion for PWRDWN
   IS_RST_INVERTED => '0',     -- Optional inversion for RST
   REF_JITTER => 0.0,          -- Reference input jitter in UI
   STARTUP_WAIT => "FALSE"     -- Delays DONE until PLL is locked
)
port map (
   CLKFBOUT => CLKFBOUT,       -- 1-bit output: Feedback clock
   CLKOUT0 => CLKOUT0,         -- 1-bit output: General Clock output
   CLKOUT0B => CLKOUT0B,       -- 1-bit output: Inverted CLKOUT0
   CLKOUT1 => CLKOUT1,         -- 1-bit output: General Clock output
   CLKOUT1B => CLKOUT1B,       -- 1-bit output: Inverted CLKOUT1
   CLKOUTPHY => CLKOUTPHY,     -- 1-bit output: Bitslice clock
   LOCKED => LOCKED,           -- 1-bit output: LOCK
   CLKFBIN => CLKFBIN,         -- 1-bit input: Feedback clock
   CLKIN => CLKIN,             -- 1-bit input: Input clock
   CLKOUTPHYEN => CLKOUTPHYEN, -- 1-bit input: CLKOUTPHY enable
   PWRDWN => PWRDWN,           -- 1-bit input: Power-down
   RST => RST                  -- 1-bit input: Reset
);

-- End of PLLE4_BASE_inst instantiation

Verilog Instantiation Template


// PLLE4_BASE: Base Phase-Locked Loop (PLL)
//             UltraScale
// Xilinx HDL Language Template, version 2022.1

PLLE4_BASE #(
   .CLKFBOUT_MULT(5),          // Multiply value for all CLKOUT
   .CLKFBOUT_PHASE(0.0),       // Phase offset in degrees of CLKFB
   .CLKIN_PERIOD(0.0),         // Input clock period in ns to ps resolution (i.e., 33.333 is 30 MHz).
   .CLKOUT0_DIVIDE(1),         // Divide amount for CLKOUT0
   .CLKOUT0_DUTY_CYCLE(0.5),   // Duty cycle for CLKOUT0
   .CLKOUT0_PHASE(0.0),        // Phase offset for CLKOUT0
   .CLKOUT1_DIVIDE(1),         // Divide amount for CLKOUT1
   .CLKOUT1_DUTY_CYCLE(0.5),   // Duty cycle for CLKOUT1
   .CLKOUT1_PHASE(0.0),        // Phase offset for CLKOUT1
   .CLKOUTPHY_MODE("VCO_2X"),  // Frequency of the CLKOUTPHY
   .DIVCLK_DIVIDE(1),          // Master division value
   .IS_CLKFBIN_INVERTED(1'b0), // Optional inversion for CLKFBIN
   .IS_CLKIN_INVERTED(1'b0),   // Optional inversion for CLKIN
   .IS_PWRDWN_INVERTED(1'b0),  // Optional inversion for PWRDWN
   .IS_RST_INVERTED(1'b0),     // Optional inversion for RST
   .REF_JITTER(0.0),           // Reference input jitter in UI
   .STARTUP_WAIT("FALSE")      // Delays DONE until PLL is locked
)
PLLE4_BASE_inst (
   .CLKFBOUT(CLKFBOUT),       // 1-bit output: Feedback clock
   .CLKOUT0(CLKOUT0),         // 1-bit output: General Clock output
   .CLKOUT0B(CLKOUT0B),       // 1-bit output: Inverted CLKOUT0
   .CLKOUT1(CLKOUT1),         // 1-bit output: General Clock output
   .CLKOUT1B(CLKOUT1B),       // 1-bit output: Inverted CLKOUT1
   .CLKOUTPHY(CLKOUTPHY),     // 1-bit output: Bitslice clock
   .LOCKED(LOCKED),           // 1-bit output: LOCK
   .CLKFBIN(CLKFBIN),         // 1-bit input: Feedback clock
   .CLKIN(CLKIN),             // 1-bit input: Input clock
   .CLKOUTPHYEN(CLKOUTPHYEN), // 1-bit input: CLKOUTPHY enable
   .PWRDWN(PWRDWN),           // 1-bit input: Power-down
   .RST(RST)                  // 1-bit input: Reset
);

// End of PLLE4_BASE_inst instantiation

Related Information

  • See the UltraScale Architecture Clocking Resources User Guide (UG572).