Primitive: 48-bit Multi-Functional Arithmetic Block
- PRIMITIVE_GROUP: ARITHMETIC
- PRIMITIVE_SUBGROUP: DSP
- Families: UltraScale, UltraScale+
Introduction
This design element is a versatile, scalable, integrated block that allows for the creation of compact, high-speed, arithmetic-intensive operations, such as those seen for many DSP algorithms. Some of the functions capable within the block include multiplication, addition, subtraction, accumulation, shifting, logical operations, and pattern detection.
Port Descriptions
Port | Direction | Width | Function |
---|---|---|---|
XOROUT<7:0> | Output | 8 | Data output from Wide XOR logic function |
Cascade: Cascade Ports | |||
ACIN<29:0> | Input | 30 | Cascaded data input from ACOUT of previous DSP48E2 (multiplexed with A). If not used, tie port to all zeros. |
ACOUT<29:0> | Output | 30 | Cascaded data output to ACIN of next DSP48E2. If not used, leave unconnected. |
BCIN<17:0> | Input | 18 | Cascaded data input from BCOUT of previous DSP48E2 (multiplexed with B). If not used, tie port to all zeros. |
BCOUT<17:0> | Output | 18 | Cascaded data output to BCIN of next DSP48E2. If not used, leave unconnected. |
CARRYCASCIN | Input | 1 | Cascaded carry input from CARRYCASCOUT of previous DSP48E2. |
CARRYCASCOUT | Output | 1 | Cascaded carry output to CARRYCASCIN of next DSP48E2. This signal is internally fed back into the CARRYINSEL multiplexer input of the same DSP48E2. |
MULTSIGNIN | Input | 1 | Sign of the multiplied result from the previous DSP48E2 for MACC extension. Connect to the MULTSIGNOUT of another DSP block, or tie to ground if not used. |
MULTSIGNOUT | Output | 1 | Sign of the multiplied result cascaded to the next DSP48E2 for MACC extension. Connect to the MULTSIGNIN of another DSP block, or tie to ground if not used. |
PCIN<47:0> | Input | 48 | Cascaded data input from PCOUT of previous DSP48E2 to adder. If used, connect to PCOUT of upstream cascaded DSP48E2. If not used, tie port to all zeros. |
PCOUT<47:0> | Output | 48 | Cascaded data output to PCIN of next DSP48E2. If used, connect to PCIN of downstream cascaded DSP48E2. If not used, leave unconnected. |
Control: Control Inputs/Status Bits | |||
ALUMODE<3:0> | Input | 4 | Controls the selection of the logic function in the DSP48E2. |
CARRYINSEL<2:0> | Input | 3 | Selects the carry source.
|
CLK | Input | 1 | This port is the DSP48E2 input clock, common to all internal registers and flip-flops. |
INMODE<4:0> | Input | 5 | These five control bits select the functionality of the pre-adder, the A, B, and D inputs, and the input registers. These bits should be tied to all zeros if not used. |
OPMODE<8:0> | Input | 9 | Controls the input to the W, X, Y, and Z multiplexers in the DSP48E2 dictating the operation or function of the component. |
OVERFLOW | Output | 1 | Active-High overflow indicator when used with the appropriate setting of the pattern detector and PREG=1. |
PATTERNBDETECT | Output | 1 | Active-High match indicator between P[47:0] and the pattern bar. |
PATTERNDETECT | Output | 1 | Active-High match indicator between P[47:0] and the pattern gated by the MASK. Result arrives on the same cycle as P. |
UNDERFLOW | Output | 1 | Active-High underflow indicator when used with the appropriate setting of the pattern detector and PREG=1. |
Data: Data Ports | |||
A<29:0> | Input | 30 | Data input for pre-adder, multiplier, adder/subtracter/accumulator, ALU, or concatenation operations.
|
B<17:0> | Input | 18 | The B input of the multiplier. B[17:0] are the least significant bits (LSBs) of the A:B concatenated input to the second-stage adder/subtracter or logic function. If this port is not used, tie all bits High. |
C<47:0> | Input | 48 | Data input to the second-stage adder/subtracter, pattern detector, or logic function. If this port is not used, tie all bits High. |
CARRYIN | Input | 1 | Carry input from the device logic. |
CARRYOUT<3:0> | Output | 4 | 4-bit carry output from each 12-bit field of the accumulate/adder/logic unit. Normal 48-bit operation uses only CARRYOUT3. SIMD operation can use four carry out bits (CARRYOUT[3:0]). |
D<26:0> | Input | 27 | 27-bit data input to the pre-adder or alternative input to the multiplier. The pre-adder implements D + A as determined by the INMODE3 signal. If this port is not used, tie all bits High. |
P<47:0> | Output | 48 | Data output from second stage adder/subtracter or logic function. |
Reset/Clock Enable: Reset/Clock Enable Inputs. | |||
CEAD | Input | 1 | Active-High, clock enable for the pre-adder output AD pipeline register. Tie to logic one if not used and ADREG=1. Tie to logic zero if ADREG=0. |
CEALUMODE | Input | 1 | Active-High, clock enable for ALUMODE (control inputs) registers (ALUMODEREG=1). Tie to logic one if not used. |
CEA1 | Input | 1 | Active-High, clock enable for the first A (input) register. This port is only used if AREG=2 or INMODE0 = 1. When two registers are used, this is the first sequentially. When Dynamic AB Access is used, this clock enable is applied for INMODE[0]=1. If the A port is not used, tie Low. |
CEA2 | Input | 1 | Active-High, clock enable for the second A (input) register. When two registers are used, this is the second sequentially. When one register is used (AREG=1), CEA2 is the clock enable. If the A port is not used, tie Low. |
CEB1 | Input | 1 | Active-High, clock enable for the first B (input) register. When two registers are used, this is the first sequentially. When Dynamic AB Access is used, this clock enable is applied for INMODE[4]=1. If the B port is not used, tie Low. |
CEB2 | Input | 1 | Active-High, clock enable for the second B (input) register. This port is only used if BREG=1 or 2. Tie to logic one if not used and BREG=1 or 2. Tie to logic zero if BREG=0. When two registers are used, this is the second sequentially. When one register is used (BREG=1), CEB2 is the clock enable. |
CEC | Input | 1 | Active-High, clock enable for the C (input) register (CREG=1). If the C port is not used, tie Low. |
CECARRYIN | Input | 1 | Active-High, clock enable for the CARRYIN (input from fabric) register (CARRYINREG=1). Tie to logic one if not used. |
CECTRL | Input | 1 | Active-High, clock enable for the OPMODE and CARRYINSEL (control inputs) registers (OPMODEREG=1 or CARRYINSELREG=1). Tie to logic one if not used. |
CED | Input | 1 | Active-High, clock enable for the D (input) registers (DREG=1). If the D port is not used, tie Low. |
CEINMODE | Input | 1 | Active-High, clock enable for the INMODE control input registers (INMODEREG=1). Tie to logic one if not used. |
CEM | Input | 1 | Active-High, Clock enable for the post-multiply M (pipeline) register and the internal multiply round CARRYIN register (MREG=1). Tie to logic one if not used. |
CEP | Input | 1 | Active-High, clock enable for the P (output) register (PREG=1). Tie to logic one if not used. |
RSTA | Input | 1 | Synchronous reset for both A (input) registers (AREG=1 or 2). Polarity is determined by the IS_RSTA_INVERTED attribute. Tie to logic zero if A port is not used. |
RSTALLCARRYIN | Input | 1 | Synchronous reset for the Carry (internal path) and the CARRYIN registers (CARRYINREG=1). Polarity is determined by the IS_RSTALLCARRYIN_INVERTED attribute. Tie to logic zero if not used. |
RSTALUMODE | Input | 1 | Synchronous Reset for ALUMODE (control inputs) registers (ALUMODEREG=1). Polarity is determined by the IS_RSTALUMODE_INVERTED attribute. Tie to logic zero if not used. |
RSTB | Input | 1 | Synchronous Reset for both B (input) registers (BREG=1 or 2). Polarity is determined by the IS_RSTB_INVERTED attribute. Tie to logic zero if B port is not used. |
RSTC | Input | 1 | Synchronous reset for the C (input) registers (CREG=1). Polarity is determined by the IS_RSTC_INVERTED attribute. Tie to logic zero if C port is not used. |
RSTCTRL | Input | 1 | Synchronous reset for OPMODE and CARRYINSEL (control inputs) registers (OPMODEREG=1 and/or CARRYINSELREG=1). Polarity is determined by the IS_RSTCTRL_INVERTED attribute. Tie to logic zero if not used. |
RSTD | Input | 1 | Synchronous reset for the D (input) register and for the pre-adder (output) AD pipeline register (DREG=1 and/or ADREG=1). Polarity is determined by the IS_RSTD_INVERTED attribute. Tie to logic zero if B port is not used. |
RSTINMODE | Input | 1 | Synchronous reset for the INMODE (control input) registers (INMODEREG=1). Polarity is determined by the IS_RSTINMODE_INVERTED attribute. Tie to logic zero if not used. |
RSTM | Input | 1 | Synchronous reset for the M (pipeline) registers (MREG=1). Polarity is determined by the IS_RSTM_INVERTED attribute. Tie to logic zero if not used. |
RSTP | Input | 1 | Synchronous reset for the P (output) registers (PREG=1). Polarity is determined by the IS_RSTP_INVERTED attribute. Tie to logic zero if not used. |
Design Entry Method
Instantiation | Yes |
Inference | Recommended |
IP and IP Integrator Catalog | Yes |
Available Attributes
Attribute | Type | Allowed Values | Default | Description |
---|---|---|---|---|
Feature Control Attributes: Specifies how to use a given input data port (that is, from general fabric, "DIRECT", or from another DSP48E2, "CASCADE"). | ||||
A_INPUT | STRING | "DIRECT", "CASCADE" | "DIRECT" | Selects the input to the A port between parallel input ("DIRECT") or the cascaded input from the previous DSP48E2 ("CASCADE"). |
AMULTSEL | STRING | "A", "AD" | "A" | Selects the input to the 27-bit A input of the multiplier. |
B_INPUT | STRING | "DIRECT", "CASCADE" | "DIRECT" | Selects the input to the B port between parallel input ("DIRECT") or the cascaded input from the previous DSP48E2 ("CASCADE"). |
BMULTSEL | STRING | "B", "AD" | "B" | Selects the input to the 18-bit B input of the multiplier. |
PREADDINSEL | STRING | "A", "B" | "A" | Selects the input to be added with D in the pre-adder. |
RND | HEX | Any 48-bit HEX value | All zeroes | Rounding Constant into the WMUX. |
USE_MULT | STRING | "MULTIPLY", "DYNAMIC", "NONE" | "MULTIPLY" | Selects usage of the multiplier.
|
USE_SIMD | STRING | "ONE48", "FOUR12", "TWO24" | "ONE48" | Selects the mode of operation for the adder/subtracter. The attribute setting can be one 48-bit adder mode ("ONE48"), two 24- bit adder mode ("TWO24"), or four 12-bit adder mode ("FOUR12"). Typical Multiply-Add operations are supported when the mode is set to "ONE48". When "TWO24" or "FOUR12" mode is selected, the multiplier must not be used, and USE_MULT must be set to "NONE". |
USE_WIDEXOR | STRING | "FALSE", "TRUE" | "FALSE" | Determines whether the Wide XOR is used or not. |
XORSIMD | STRING | "XOR24_48_96", "XOR12" | "XOR24_48_96" | Selects the mode of operation for the Wide XOR. The attribute setting can be one 96-bit, two 48-bit four 24-bit XOR modes (XOR24_48_96), or eight 12-bit XOR mode (XOR12). |
Pattern Detector Attributes: Pattern Detection Configuration/Specification | ||||
AUTORESET_PATDET | STRING | "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH" | "NO_RESET" | Automatically resets the P Register (accumulated value or
counter value) on the next clock cycle, if a pattern detect event
has occurred on this clock cycle. The "RESET_MATCH" and
"RESET_NOT_MATCH" settings distinguish between whether
the DSP48E2 should cause an auto reset of the P Register
on the next cycle:
|
AUTORESET_PRIORITY | STRING | "RESET", "CEP" | "RESET" | When using the AUTORESET_PATDET feature, defines priority of AUTORESET versus clock enable (CEP). |
MASK | HEX | Any 48-bit HEX value | 48'h3fffffffffff | This 48-bit value is used to mask out certain bits during a
pattern detection.
|
PATTERN | HEX | Any 48-bit HEX value | All zeroes | This 48-bit value is used in the pattern detector. |
SEL_MASK | STRING | "MASK", "C", "ROUNDING_MODE1", "ROUNDING_MODE2" | "MASK" | Selects the mask to be used for the pattern detector. The C and MASK settings are for standard uses of the pattern detector (counter, overflow detection, etc.). ROUNDING_MODE1 (C-bar left shifted by 1) and ROUNDING_MODE2 (C-bar left shifted by 2) select special masks based off of the optionally registered C port. These rounding modes can be used to implement convergent rounding in the DSP48E2 using the pattern detector. |
SEL_PATTERN | STRING | "PATTERN", "C" | "PATTERN" | Selects the input source for the pattern field. The input source can be a 48-bit dynamic C input or a 48-bit static PATTERN attribute field. |
USE_PATTERN_DETECT | STRING | "NO_PATDET", "PATDET" | "NO_PATDET" | Selects whether the pattern detector and related features are used ("PATDET") or not used ("NO_PATDET"). This attribute is used for speed specification and Simulation Model purposes only. |
Programmable Inversion Attributes: Specifies whether or not to use the optional inversions on specific pins for this component to change the active polarity of the pin function. When set to 1 on a clock pin (CLK), this component clocks on the negative edge. When set to 1 on other pins, it changes the function to behave active-Low rather than active-High. For pins that are buses, the bit-width of this attribute should match that of the bit-width of the associated pins and a binary value specifies which inverters to use and which to bypass. If an external inverter is specified on one of these associated pins, the Vivado Design Suite will automatically set this attribute during the opt_design stage so that additional logic is not necessary for changing the input polarity. | ||||
IS_ALUMODE_INVERTED | BINARY | 4'b0000 to 4'b1111 | 4'b0000 | Specifies whether or not to use the optional inversions on the individual ALUMODE pins of this component. |
IS_CARRYIN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CARRYIN pin of this component. |
IS_CLK_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the CLK pin of this component. |
IS_INMODE_INVERTED | BINARY | 5'b00000 to 5'b11111 | 5'b00000 | Specifies whether or not to use the optional inversions on the individual INMODE pins of this component. |
IS_OPMODE_INVERTED | BINARY | 9'b000000000 to 9'b111111111 | 9'b000000000 | Specifies whether or not to use the optional inversions on the individual OPMODE pins of this component. |
IS_RSTA_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTA pin of this component. |
IS_RSTALLCARRYIN_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTALLCARRYIN pin of this component. |
IS_RSTALUMODE_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTALUMODE pin of this component. |
IS_RSTB_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTB pin of this component. |
IS_RSTC_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTC pin of this component. |
IS_RSTCTRL_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTCTRL pin of this component. |
IS_RSTD_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTD pin of this component. |
IS_RSTINMODE_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTINMODE pin of this component. |
IS_RSTM_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTM pin of this component. |
IS_RSTP_INVERTED | BINARY | 1'b0 to 1'b1 | 1'b0 | Specifies whether or not to use the optional inversion on the RSTP pin of this component. |
Register Control Attributes: Pipeline Register Configuration/Specification. | ||||
ACASCREG | DECIMAL | 1, 0, 2 | 1 | In conjunction with AREG, selects the number of A input
registers on the A cascade path, ACOUT. This attribute must be
equal to or one less than the AREG value:
|
ADREG | DECIMAL | 1, 0 | 1 | Selects the number of pre-adder pipeline registers. |
ALUMODEREG | DECIMAL | 1, 0 | 1 | Selects the number of ALUMODE input registers. |
AREG | DECIMAL | 1, 0, 2 | 1 | Selects the number of A input pipeline registers. If A port is not in use, set to 1. |
BCASCREG | DECIMAL | 1, 0, 2 | 1 | In conjunction with BREG, selects the number of B input
registers on the B cascade path, BCOUT. This attribute must be
equal to or one less than the BREG value:
|
BREG | DECIMAL | 1, 0, 2 | 1 | Selects the number of B input registers If B port is not in use, set to 1. |
CARRYINREG | DECIMAL | 1, 0 | 1 | Selects the number of CARRYIN input registers. |
CARRYINSELREG | DECIMAL | 1, 0 | 1 | Selects the number of CARRYINSEL input registers. |
CREG | DECIMAL | 1, 0 | 1 | Selects the number of C input registers. If C port is not in use, set to 1. |
DREG | DECIMAL | 1, 0 | 1 | Selects the number of D input registers. If D port is not in use, set to 1. |
INMODEREG | DECIMAL | 1, 0 | 1 | Selects the number of INMODE input registers. |
MREG | DECIMAL | 1, 0 | 1 | Selects the number of multiplier output (M) pipeline register stages. |
OPMODEREG | DECIMAL | 1, 0 | 1 | Selects the number of OPMODE input registers. |
PREG | DECIMAL | 1, 0 | 1 | Selects the number of P output registers. The registered outputs will include CARRYOUT, CARRYCASCOUT, MULTSIGNOUT, PATTERNB_DETECT, PATTERN_DETECT, and PCOUT. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- DSP48E2: 48-bit Multi-Functional Arithmetic Block
-- UltraScale
-- Xilinx HDL Language Template, version 2022.1
DSP48E2_inst : DSP48E2
generic map (
-- Feature Control Attributes: Data Path Selection
AMULTSEL => "A", -- Selects A input to multiplier (A, AD)
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
BMULTSEL => "B", -- Selects B input to multiplier (AD, B)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
PREADDINSEL => "A", -- Selects input to pre-adder (A, B)
RND => X"000000000000", -- Rounding Constant
USE_MULT => "MULTIPLY", -- Select multiplier usage (DYNAMIC, MULTIPLY, NONE)
USE_SIMD => "ONE48", -- SIMD selection (FOUR12, ONE48, TWO24)
USE_WIDEXOR => "FALSE", -- Use the Wide XOR function (FALSE, TRUE)
XORSIMD => "XOR24_48_96", -- Mode of operation for the Wide XOR (XOR12, XOR24_48_96)
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- NO_RESET, RESET_MATCH, RESET_NOT_MATCH
AUTORESET_PRIORITY => "RESET", -- Priority of AUTORESET vs. CEP (CEP, RESET).
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- C, MASK, ROUNDING_MODE1, ROUNDING_MODE2
SEL_PATTERN => "PATTERN", -- Select pattern value (C, PATTERN)
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect (NO_PATDET, PATDET)
-- Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
IS_ALUMODE_INVERTED => "0000", -- Optional inversion for ALUMODE
IS_CARRYIN_INVERTED => '0', -- Optional inversion for CARRYIN
IS_CLK_INVERTED => '0', -- Optional inversion for CLK
IS_INMODE_INVERTED => "00000", -- Optional inversion for INMODE
IS_OPMODE_INVERTED => "000000000", -- Optional inversion for OPMODE
IS_RSTALLCARRYIN_INVERTED => '0', -- Optional inversion for RSTALLCARRYIN
IS_RSTALUMODE_INVERTED => '0', -- Optional inversion for RSTALUMODE
IS_RSTA_INVERTED => '0', -- Optional inversion for RSTA
IS_RSTB_INVERTED => '0', -- Optional inversion for RSTB
IS_RSTCTRL_INVERTED => '0', -- Optional inversion for RSTCTRL
IS_RSTC_INVERTED => '0', -- Optional inversion for RSTC
IS_RSTD_INVERTED => '0', -- Optional inversion for RSTD
IS_RSTINMODE_INVERTED => '0', -- Optional inversion for RSTINMODE
IS_RSTM_INVERTED => '0', -- Optional inversion for RSTM
IS_RSTP_INVERTED => '0', -- Optional inversion for RSTP
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0-2)
ADREG => 1, -- Pipeline stages for pre-adder (0-1)
ALUMODEREG => 1, -- Pipeline stages for ALUMODE (0-1)
AREG => 1, -- Pipeline stages for A (0-2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0-2)
BREG => 1, -- Pipeline stages for B (0-2)
CARRYINREG => 1, -- Pipeline stages for CARRYIN (0-1)
CARRYINSELREG => 1, -- Pipeline stages for CARRYINSEL (0-1)
CREG => 1, -- Pipeline stages for C (0-1)
DREG => 1, -- Pipeline stages for D (0-1)
INMODEREG => 1, -- Pipeline stages for INMODE (0-1)
MREG => 1, -- Multiplier pipeline stages (0-1)
OPMODEREG => 1, -- Pipeline stages for OPMODE (0-1)
PREG => 1 -- Number of pipeline stages for P (0-1)
)
port map (
-- Cascade outputs: Cascade Ports
ACOUT => ACOUT, -- 30-bit output: A port cascade
BCOUT => BCOUT, -- 18-bit output: B cascade
CARRYCASCOUT => CARRYCASCOUT, -- 1-bit output: Cascade carry
MULTSIGNOUT => MULTSIGNOUT, -- 1-bit output: Multiplier sign cascade
PCOUT => PCOUT, -- 48-bit output: Cascade output
-- Control outputs: Control Inputs/Status Bits
OVERFLOW => OVERFLOW, -- 1-bit output: Overflow in add/acc
PATTERNBDETECT => PATTERNBDETECT, -- 1-bit output: Pattern bar detect
PATTERNDETECT => PATTERNDETECT, -- 1-bit output: Pattern detect
UNDERFLOW => UNDERFLOW, -- 1-bit output: Underflow in add/acc
-- Data outputs: Data Ports
CARRYOUT => CARRYOUT, -- 4-bit output: Carry
P => P, -- 48-bit output: Primary data
XOROUT => XOROUT, -- 8-bit output: XOR data
-- Cascade inputs: Cascade Ports
ACIN => ACIN, -- 30-bit input: A cascade data
BCIN => BCIN, -- 18-bit input: B cascade
CARRYCASCIN => CARRYCASCIN, -- 1-bit input: Cascade carry
MULTSIGNIN => MULTSIGNIN, -- 1-bit input: Multiplier sign cascade
PCIN => PCIN, -- 48-bit input: P cascade
-- Control inputs: Control Inputs/Status Bits
ALUMODE => ALUMODE, -- 4-bit input: ALU control
CARRYINSEL => CARRYINSEL, -- 3-bit input: Carry select
CLK => CLK, -- 1-bit input: Clock
INMODE => INMODE, -- 5-bit input: INMODE control
OPMODE => OPMODE, -- 9-bit input: Operation mode
-- Data inputs: Data Ports
A => A, -- 30-bit input: A data
B => B, -- 18-bit input: B data
C => C, -- 48-bit input: C data
CARRYIN => CARRYIN, -- 1-bit input: Carry-in
D => D, -- 27-bit input: D data
-- Reset/Clock Enable inputs: Reset/Clock Enable Inputs
CEA1 => CEA1, -- 1-bit input: Clock enable for 1st stage AREG
CEA2 => CEA2, -- 1-bit input: Clock enable for 2nd stage AREG
CEAD => CEAD, -- 1-bit input: Clock enable for ADREG
CEALUMODE => CEALUMODE, -- 1-bit input: Clock enable for ALUMODE
CEB1 => CEB1, -- 1-bit input: Clock enable for 1st stage BREG
CEB2 => CEB2, -- 1-bit input: Clock enable for 2nd stage BREG
CEC => CEC, -- 1-bit input: Clock enable for CREG
CECARRYIN => CECARRYIN, -- 1-bit input: Clock enable for CARRYINREG
CECTRL => CECTRL, -- 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG
CED => CED, -- 1-bit input: Clock enable for DREG
CEINMODE => CEINMODE, -- 1-bit input: Clock enable for INMODEREG
CEM => CEM, -- 1-bit input: Clock enable for MREG
CEP => CEP, -- 1-bit input: Clock enable for PREG
RSTA => RSTA, -- 1-bit input: Reset for AREG
RSTALLCARRYIN => RSTALLCARRYIN, -- 1-bit input: Reset for CARRYINREG
RSTALUMODE => RSTALUMODE, -- 1-bit input: Reset for ALUMODEREG
RSTB => RSTB, -- 1-bit input: Reset for BREG
RSTC => RSTC, -- 1-bit input: Reset for CREG
RSTCTRL => RSTCTRL, -- 1-bit input: Reset for OPMODEREG and CARRYINSELREG
RSTD => RSTD, -- 1-bit input: Reset for DREG and ADREG
RSTINMODE => RSTINMODE, -- 1-bit input: Reset for INMODEREG
RSTM => RSTM, -- 1-bit input: Reset for MREG
RSTP => RSTP -- 1-bit input: Reset for PREG
);
-- End of DSP48E2_inst instantiation
Verilog Instantiation Template
// DSP48E2: 48-bit Multi-Functional Arithmetic Block
// UltraScale
// Xilinx HDL Language Template, version 2022.1
DSP48E2 #(
// Feature Control Attributes: Data Path Selection
.AMULTSEL("A"), // Selects A input to multiplier (A, AD)
.A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
.BMULTSEL("B"), // Selects B input to multiplier (AD, B)
.B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
.PREADDINSEL("A"), // Selects input to pre-adder (A, B)
.RND(48'h000000000000), // Rounding Constant
.USE_MULT("MULTIPLY"), // Select multiplier usage (DYNAMIC, MULTIPLY, NONE)
.USE_SIMD("ONE48"), // SIMD selection (FOUR12, ONE48, TWO24)
.USE_WIDEXOR("FALSE"), // Use the Wide XOR function (FALSE, TRUE)
.XORSIMD("XOR24_48_96"), // Mode of operation for the Wide XOR (XOR12, XOR24_48_96)
// Pattern Detector Attributes: Pattern Detection Configuration
.AUTORESET_PATDET("NO_RESET"), // NO_RESET, RESET_MATCH, RESET_NOT_MATCH
.AUTORESET_PRIORITY("RESET"), // Priority of AUTORESET vs. CEP (CEP, RESET).
.MASK(48'h3fffffffffff), // 48-bit mask value for pattern detect (1=ignore)
.PATTERN(48'h000000000000), // 48-bit pattern match for pattern detect
.SEL_MASK("MASK"), // C, MASK, ROUNDING_MODE1, ROUNDING_MODE2
.SEL_PATTERN("PATTERN"), // Select pattern value (C, PATTERN)
.USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect (NO_PATDET, PATDET)
// Programmable Inversion Attributes: Specifies built-in programmable inversion on specific pins
.IS_ALUMODE_INVERTED(4'b0000), // Optional inversion for ALUMODE
.IS_CARRYIN_INVERTED(1'b0), // Optional inversion for CARRYIN
.IS_CLK_INVERTED(1'b0), // Optional inversion for CLK
.IS_INMODE_INVERTED(5'b00000), // Optional inversion for INMODE
.IS_OPMODE_INVERTED(9'b000000000), // Optional inversion for OPMODE
.IS_RSTALLCARRYIN_INVERTED(1'b0), // Optional inversion for RSTALLCARRYIN
.IS_RSTALUMODE_INVERTED(1'b0), // Optional inversion for RSTALUMODE
.IS_RSTA_INVERTED(1'b0), // Optional inversion for RSTA
.IS_RSTB_INVERTED(1'b0), // Optional inversion for RSTB
.IS_RSTCTRL_INVERTED(1'b0), // Optional inversion for RSTCTRL
.IS_RSTC_INVERTED(1'b0), // Optional inversion for RSTC
.IS_RSTD_INVERTED(1'b0), // Optional inversion for RSTD
.IS_RSTINMODE_INVERTED(1'b0), // Optional inversion for RSTINMODE
.IS_RSTM_INVERTED(1'b0), // Optional inversion for RSTM
.IS_RSTP_INVERTED(1'b0), // Optional inversion for RSTP
// Register Control Attributes: Pipeline Register Configuration
.ACASCREG(1), // Number of pipeline stages between A/ACIN and ACOUT (0-2)
.ADREG(1), // Pipeline stages for pre-adder (0-1)
.ALUMODEREG(1), // Pipeline stages for ALUMODE (0-1)
.AREG(1), // Pipeline stages for A (0-2)
.BCASCREG(1), // Number of pipeline stages between B/BCIN and BCOUT (0-2)
.BREG(1), // Pipeline stages for B (0-2)
.CARRYINREG(1), // Pipeline stages for CARRYIN (0-1)
.CARRYINSELREG(1), // Pipeline stages for CARRYINSEL (0-1)
.CREG(1), // Pipeline stages for C (0-1)
.DREG(1), // Pipeline stages for D (0-1)
.INMODEREG(1), // Pipeline stages for INMODE (0-1)
.MREG(1), // Multiplier pipeline stages (0-1)
.OPMODEREG(1), // Pipeline stages for OPMODE (0-1)
.PREG(1) // Number of pipeline stages for P (0-1)
)
DSP48E2_inst (
// Cascade outputs: Cascade Ports
.ACOUT(ACOUT), // 30-bit output: A port cascade
.BCOUT(BCOUT), // 18-bit output: B cascade
.CARRYCASCOUT(CARRYCASCOUT), // 1-bit output: Cascade carry
.MULTSIGNOUT(MULTSIGNOUT), // 1-bit output: Multiplier sign cascade
.PCOUT(PCOUT), // 48-bit output: Cascade output
// Control outputs: Control Inputs/Status Bits
.OVERFLOW(OVERFLOW), // 1-bit output: Overflow in add/acc
.PATTERNBDETECT(PATTERNBDETECT), // 1-bit output: Pattern bar detect
.PATTERNDETECT(PATTERNDETECT), // 1-bit output: Pattern detect
.UNDERFLOW(UNDERFLOW), // 1-bit output: Underflow in add/acc
// Data outputs: Data Ports
.CARRYOUT(CARRYOUT), // 4-bit output: Carry
.P(P), // 48-bit output: Primary data
.XOROUT(XOROUT), // 8-bit output: XOR data
// Cascade inputs: Cascade Ports
.ACIN(ACIN), // 30-bit input: A cascade data
.BCIN(BCIN), // 18-bit input: B cascade
.CARRYCASCIN(CARRYCASCIN), // 1-bit input: Cascade carry
.MULTSIGNIN(MULTSIGNIN), // 1-bit input: Multiplier sign cascade
.PCIN(PCIN), // 48-bit input: P cascade
// Control inputs: Control Inputs/Status Bits
.ALUMODE(ALUMODE), // 4-bit input: ALU control
.CARRYINSEL(CARRYINSEL), // 3-bit input: Carry select
.CLK(CLK), // 1-bit input: Clock
.INMODE(INMODE), // 5-bit input: INMODE control
.OPMODE(OPMODE), // 9-bit input: Operation mode
// Data inputs: Data Ports
.A(A), // 30-bit input: A data
.B(B), // 18-bit input: B data
.C(C), // 48-bit input: C data
.CARRYIN(CARRYIN), // 1-bit input: Carry-in
.D(D), // 27-bit input: D data
// Reset/Clock Enable inputs: Reset/Clock Enable Inputs
.CEA1(CEA1), // 1-bit input: Clock enable for 1st stage AREG
.CEA2(CEA2), // 1-bit input: Clock enable for 2nd stage AREG
.CEAD(CEAD), // 1-bit input: Clock enable for ADREG
.CEALUMODE(CEALUMODE), // 1-bit input: Clock enable for ALUMODE
.CEB1(CEB1), // 1-bit input: Clock enable for 1st stage BREG
.CEB2(CEB2), // 1-bit input: Clock enable for 2nd stage BREG
.CEC(CEC), // 1-bit input: Clock enable for CREG
.CECARRYIN(CECARRYIN), // 1-bit input: Clock enable for CARRYINREG
.CECTRL(CECTRL), // 1-bit input: Clock enable for OPMODEREG and CARRYINSELREG
.CED(CED), // 1-bit input: Clock enable for DREG
.CEINMODE(CEINMODE), // 1-bit input: Clock enable for INMODEREG
.CEM(CEM), // 1-bit input: Clock enable for MREG
.CEP(CEP), // 1-bit input: Clock enable for PREG
.RSTA(RSTA), // 1-bit input: Reset for AREG
.RSTALLCARRYIN(RSTALLCARRYIN), // 1-bit input: Reset for CARRYINREG
.RSTALUMODE(RSTALUMODE), // 1-bit input: Reset for ALUMODEREG
.RSTB(RSTB), // 1-bit input: Reset for BREG
.RSTC(RSTC), // 1-bit input: Reset for CREG
.RSTCTRL(RSTCTRL), // 1-bit input: Reset for OPMODEREG and CARRYINSELREG
.RSTD(RSTD), // 1-bit input: Reset for DREG and ADREG
.RSTINMODE(RSTINMODE), // 1-bit input: Reset for INMODEREG
.RSTM(RSTM), // 1-bit input: Reset for MREG
.RSTP(RSTP) // 1-bit input: Reset for PREG
);
// End of DSP48E2_inst instantiation
Related Information
- See the UltraScale Architecture DSP Slice User Guide (UG579).