RX_BITSLICE - 2022.1 English

Primitive: RX_BITSLICE for input using Native Mode

PRIMITIVE_GROUP: I/O
PRIMITIVE_SUBGROUP: BITSLICE
Families: UltraScale, UltraScale+

Introduction

In native mode, the RX_BITSLICE contains deserialization logic and 512-tap input delay (IDELAY) that can be continuously adjusted for VT variation. The RX_BITSLICE contains deserialization logic for 1:4 or 1:8 deserialization and a shallow FIFO to allow connection to another clock domain.

Port Descriptions

Port	Direction	Width	Function
CE	Input	1	Clock enable for RX_BITSLICE IDELAY register clock.
CE_EXT	Input	1	Optional extended (cascaded delay) clock enable for IDELAY register clock.
CLK	Input	1	Clock used to sample LOAD, CE, INC.
CLK_EXT	Input	1	Optional extended (cascaded delay) delay clock used to sample LOAD, CE, and INC.
CNTVALUEIN<8:0>	Input	9	Counter value from internal device logic for tap value to be loaded dynamically.
CNTVALUEIN_EXT<8:0>	Input	9	Optional extended (cascaded delay) counter value from internal device logic for tap value to be loaded dynamically.
CNTVALUEOUT<8:0>	Output	9	Counter value to going the internal device logic for monitoring tap value.
CNTVALUEOUT_EXT<8:0>	Output	9	Optional extended (cascaded delay) counter value going to the internal device logic for monitoring tap value.
DATAIN	Input	1	Input signal from IBUF.
EN_VTC	Input	1	Enables IDELAYCTRL to keep stable delay over VT when set to HIGH. VT compensation disabled when set to LOW.
EN_VTC_EXT	Input	1	Enables IDELAYCTRL to keep stable delay over VT of the cascaded delay when set to HIGH. VT compensation disabled when set to LOW.
FIFO_EMPTY	Output	1	FIFO empty flag for the FIFO of this bit.
FIFO_RD_CLK	Input	1	FIFO read clock for the FIFO of this bit.
FIFO_RD_EN	Input	1	FIFO read enable for the FIFO of this bit.
FIFO_WRCLK_OUT	Output	1	FIFO source synchronous write clock out to the device logic. Only valid for RX_BITSLICE 0. Currently not supported, do not connect.
INC	Input	1	Increment the current delay tap setting.
INC_EXT	Input	1	Optional extended (cascaded delay) increments the current delay tap setting.
LOAD	Input	1	Load the CNTVALUEIN tap setting.
LOAD_EXT	Input	1	Optional extended (cascaded delay) load the CNTVALUEIN_EXT tap setting.
Q<7:0>	Output	8	Registered output data from FIFO.
RST	Input	1	Asynchronous assert, synchronous deassert for RX_BITSLICE ISERDES.
RST_DLY	Input	1	Reset the internal DELAY value to DELAY_VALUE.
RST_DLY_EXT	Input	1	Optional extended (cascaded delay) reset delay to DELAY_VALUE_EXT.
RX_BIT_CTRL_IN<39:0>	Input	40	Input bus from BITSLICE_CONTROL.
RX_BIT_CTRL_OUT<39:0>	Output	40	Output bus to BITSLICE_CONTROL.
TX_BIT_CTRL_IN<39:0>	Input	40	Input bus from BITSLICE_CONTROL.
TX_BIT_CTRL_OUT<39:0>	Output	40	Output bus to BITSLICE_CONTROL.

Design Entry Method

Instantiation	Yes
Inference	No
IP and IP Integrator Catalog	Yes

Available Attributes

Attribute	Type	Allowed Values	Default	Description
CASCADE	STRING	"FALSE", "TRUE"	"FALSE"	"TRUE": Enables cascading of IDELAY and ODELAY lines to get a total of 2.5ns delay. Extended delay controlled by the _EXT pins. "FALSE": Only use IDELAY delay line with a maximum of 1.25ns delay.
DATA_TYPE	STRING	"DATA", "CLOCK", "DATA_AND_CLOCK", "SERIAL"	"DATA"	Defines whether the input pin is carrying a clock signal, a data signal, or clock signal that is also used as data.
DATA_WIDTH	DECIMAL	8, 4	8	Defines the width of the serial-to-parallel converter. Legal data widths are 4 and 8.
DELAY_FORMAT	STRING	"TIME", "COUNT"	"TIME"	Sets the units of DELAY_VALUE of the RX_BITSLICE IDELAY. Use TIME when DELAY_TYPE is FIXED. Use COUNT when DELAY_TYPE is VARIABLE or VAR_LOAD. "TIME": RX_BITSLICE IDELAY DELAY_VALUE is specified in ps. "COUNT": RX_BITSLICE IDELAY DELAY_VALUE is specified in taps.
DELAY_TYPE	STRING	"FIXED", "VARIABLE", "VAR_LOAD"	"FIXED"	Sets the type of tap delay line. "FIXED": Sets a static delay value. "VARIABLE": Dynamically adjust (increment/decrement) delay value. "VAR_LOAD": Dynamically loads tap values.
DELAY_VALUE	DECIMAL	0 to 1250	0	Specifies the fixed delay in ps when using FIXED DELAY_TYPE. Specifies value upon reset when using VARIABLE or VAR_LOAD.
DELAY_VALUE_EXT	DECIMAL	0 to 1250	0	Value of the extended input delay value in ps.
FIFO_SYNC_MODE	STRING	"FALSE", "TRUE"	"FALSE"	Attribute defining the relationship between FIFO_WRCLK_OUT and FIFO_RD_CLK. Always set this attribute to FALSE. TRUE is reserved for later use.
IS_CLK_EXT_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether the clock CLK_EXT pin is active-High or active-Low.
IS_CLK_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether the clock CLK pin is active-High or active-Low.
IS_RST_DLY_EXT_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether the reset RST_DLY_EXT pin is active-High or active-Low.
IS_RST_DLY_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether the reset RST_DLY pin is active-High or active-Low.
IS_RST_INVERTED	BINARY	1'b0 to 1'b1	1'b0	Specifies whether the reset RST pin is active-High or active-Low.
REFCLK_FREQUENCY	1 significant digit FLOAT	200.0 to 2667.0	300.0	Specification of the reference clock frequency in MHz.
SIM_DEVICE	STRING	"7SERIES", "ULTRASCALE"	"ULTRASCALE"	Set the device version for simulation functionality.
UPDATE_MODE	STRING	"ASYNC", "MANUAL", "SYNC"	"ASYNC"	"ASYNC": Updates are increments or decrements to the delay value independent of the data being received. "SYNC": Updates require that data input transitions to synchronously update the delay with the data input edges. "MANUAL": Updates take effect when both LOAD and CE are asserted after the LOAD and CNTVALUEIN signals are used to load the new CNTVALUE.
UPDATE_MODE_EXT	STRING	"ASYNC", "MANUAL", "SYNC"	"ASYNC"	"ASYNC": Updates are increments or decrements to the delay value independent of the data being received. "SYNC": Updates require that data input transitions to synchronously update the delay with the data input edges. "MANUAL": Updates take effect when both LOAD and CE are asserted after the LOAD and CNTVALUEIN signals are used to load the new CNTVALUE.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- RX_BITSLICE: RX_BITSLICE for input using Native Mode
--              UltraScale
-- Xilinx HDL Language Template, version 2022.1

RX_BITSLICE_inst : RX_BITSLICE
generic map (
   CASCADE => "FALSE",              -- Enables cascading of IDELAY and ODELAY lines
   DATA_TYPE => "DATA",             -- Defines what the input pin is carrying (CLOCK, DATA, DATA_AND_CLOCK,
                                    -- SERIAL)
   DATA_WIDTH => 8,                 -- Defines the width of the serial-to-parallel converter (4-8)
   DELAY_FORMAT => "TIME",          -- Units of the DELAY_VALUE (COUNT, TIME)
   DELAY_TYPE => "FIXED",           -- Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
   DELAY_VALUE => 0,                -- Input delay value setting in ps
   DELAY_VALUE_EXT => 0,            -- Value of the extended input delay value in ps
   FIFO_SYNC_MODE => "FALSE",       -- Always set to FALSE. TRUE is reserved for later use.
   IS_CLK_EXT_INVERTED => '0',      -- Optional inversion for CLK_EXT
   IS_CLK_INVERTED => '0',          -- Optional inversion for CLK
   IS_RST_DLY_EXT_INVERTED => '0',  -- Optional inversion for RST_DLY_EXT
   IS_RST_DLY_INVERTED => '0',      -- Optional inversion for RST_DLY
   IS_RST_INVERTED => '0',          -- Optional inversion for RST
   REFCLK_FREQUENCY => 300.0,       -- Specification of the reference clock frequency in MHz (200.0-2667.0)
   SIM_DEVICE => "ULTRASCALE_PLUS", -- Set the device version for simulation functionality (ULTRASCALE,
                                    -- ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
   UPDATE_MODE => "ASYNC",          -- Determines when updates to the delay will take effect (ASYNC, MANUAL,
                                    -- SYNC)
   UPDATE_MODE_EXT => "ASYNC"       -- Determines when updates to the extended input delay will take effect
                                    -- (ASYNC, MANUAL, SYNC)
)
port map (
   CNTVALUEOUT => CNTVALUEOUT,         -- 9-bit output: Counter value to device logic
   CNTVALUEOUT_EXT => CNTVALUEOUT_EXT, -- 9-bit output: Optional extended (cascaded delay) counter value
                                       -- going to the device logic

   FIFO_EMPTY => FIFO_EMPTY,           -- 1-bit output: FIFO empty flag
   FIFO_WRCLK_OUT => FIFO_WRCLK_OUT,   -- 1-bit output: FIFO source synchronous write clock out to the
                                       -- device logic (currently unsupported, do not connect)

   Q => Q,                             -- 8-bit output: Registered output data from FIFO
   RX_BIT_CTRL_OUT => RX_BIT_CTRL_OUT, -- 40-bit output: Output bus to BITSLICE_CONTROL
   TX_BIT_CTRL_OUT => TX_BIT_CTRL_OUT, -- 40-bit output: Output bus to BITSLICE_CONTROL
   CE => CE,                           -- 1-bit input: Clock enable for IDELAY
   CE_EXT => CE_EXT,                   -- 1-bit input: Optional extended (cascaded delay) clock enable
   CLK => CLK,                         -- 1-bit input: Clock used to sample LOAD, CE, INC
   CLK_EXT => CLK_EXT,                 -- 1-bit input: Optional extended (cascaded delay) clock
   CNTVALUEIN => CNTVALUEIN,           -- 9-bit input: Counter value from device logic
   CNTVALUEIN_EXT => CNTVALUEIN_EXT,   -- 9-bit input: Optional extended (cascaded delay) counter value from
                                       -- device logic

   DATAIN => DATAIN,                   -- 1-bit input: Input signal from IBUF
   EN_VTC => EN_VTC,                   -- 1-bit input: Enable IDELAYCTRL to keep stable delay over VT
   EN_VTC_EXT => EN_VTC_EXT,           -- 1-bit input: Optional extended (cascaded delay) to keep stable
                                       -- delay over VT

   FIFO_RD_CLK => FIFO_RD_CLK,         -- 1-bit input: FIFO read clock
   FIFO_RD_EN => FIFO_RD_EN,           -- 1-bit input: FIFO read enable
   INC => INC,                         -- 1-bit input: Increment the current delay tap setting
   INC_EXT => INC_EXT,                 -- 1-bit input: Optional extended (cascaded delay) increments the
                                       -- current delay tap setting

   LOAD => LOAD,                       -- 1-bit input: Load the CNTVALUEIN tap setting
   LOAD_EXT => LOAD_EXT,               -- 1-bit input: Optional extended (cascaded delay) load the
                                       -- CNTVALUEIN_EXT tap setting

   RST => RST,                         -- 1-bit input: Asynchronous assert, synchronous deassert for
                                       -- RX_BITSLICE ISERDES

   RST_DLY => RST_DLY,                 -- 1-bit input: Reset the internal DELAY value to DELAY_VALUE
   RST_DLY_EXT => RST_DLY_EXT,         -- 1-bit input: Optional extended (cascaded delay) reset delay to
                                       -- DELAY_VALUE_EXT

   RX_BIT_CTRL_IN => RX_BIT_CTRL_IN,   -- 40-bit input: Input bus from BITSLICE_CONTROL
   TX_BIT_CTRL_IN => TX_BIT_CTRL_IN    -- 40-bit input: Input bus from BITSLICE_CONTROL
);

-- End of RX_BITSLICE_inst instantiation

Verilog Instantiation Template


// RX_BITSLICE: RX_BITSLICE for input using Native Mode
//              UltraScale
// Xilinx HDL Language Template, version 2022.1

RX_BITSLICE #(
   .CASCADE("FALSE"),              // Enables cascading of IDELAY and ODELAY lines
   .DATA_TYPE("DATA"),             // Defines what the input pin is carrying (CLOCK, DATA, DATA_AND_CLOCK,
                                   // SERIAL)
   .DATA_WIDTH(8),                 // Defines the width of the serial-to-parallel converter (4-8)
   .DELAY_FORMAT("TIME"),          // Units of the DELAY_VALUE (COUNT, TIME)
   .DELAY_TYPE("FIXED"),           // Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
   .DELAY_VALUE(0),                // Input delay value setting in ps
   .DELAY_VALUE_EXT(0),            // Value of the extended input delay value in ps
   .FIFO_SYNC_MODE("FALSE"),       // Always set to FALSE. TRUE is reserved for later use.
   .IS_CLK_EXT_INVERTED(1'b0),     // Optional inversion for CLK_EXT
   .IS_CLK_INVERTED(1'b0),         // Optional inversion for CLK
   .IS_RST_DLY_EXT_INVERTED(1'b0), // Optional inversion for RST_DLY_EXT
   .IS_RST_DLY_INVERTED(1'b0),     // Optional inversion for RST_DLY
   .IS_RST_INVERTED(1'b0),         // Optional inversion for RST
   .REFCLK_FREQUENCY(300.0),       // Specification of the reference clock frequency in MHz (200.0-2667.0)
   .SIM_DEVICE("ULTRASCALE_PLUS"), // Set the device version for simulation functionality (ULTRASCALE,
                                   // ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
   .UPDATE_MODE("ASYNC"),          // Determines when updates to the delay will take effect (ASYNC, MANUAL,
                                   // SYNC)
   .UPDATE_MODE_EXT("ASYNC")       // Determines when updates to the extended input delay will take effect
                                   // (ASYNC, MANUAL, SYNC)
)
RX_BITSLICE_inst (
   .CNTVALUEOUT(CNTVALUEOUT),         // 9-bit output: Counter value to device logic
   .CNTVALUEOUT_EXT(CNTVALUEOUT_EXT), // 9-bit output: Optional extended (cascaded delay) counter value
                                      // going to the device logic

   .FIFO_EMPTY(FIFO_EMPTY),           // 1-bit output: FIFO empty flag
   .FIFO_WRCLK_OUT(FIFO_WRCLK_OUT),   // 1-bit output: FIFO source synchronous write clock out to the device
                                      // logic (currently unsupported, do not connect)

   .Q(Q),                             // 8-bit output: Registered output data from FIFO
   .RX_BIT_CTRL_OUT(RX_BIT_CTRL_OUT), // 40-bit output: Output bus to BITSLICE_CONTROL
   .TX_BIT_CTRL_OUT(TX_BIT_CTRL_OUT), // 40-bit output: Output bus to BITSLICE_CONTROL
   .CE(CE),                           // 1-bit input: Clock enable for IDELAY
   .CE_EXT(CE_EXT),                   // 1-bit input: Optional extended (cascaded delay) clock enable
   .CLK(CLK),                         // 1-bit input: Clock used to sample LOAD, CE, INC
   .CLK_EXT(CLK_EXT),                 // 1-bit input: Optional extended (cascaded delay) clock
   .CNTVALUEIN(CNTVALUEIN),           // 9-bit input: Counter value from device logic
   .CNTVALUEIN_EXT(CNTVALUEIN_EXT),   // 9-bit input: Optional extended (cascaded delay) counter value from
                                      // device logic

   .DATAIN(DATAIN),                   // 1-bit input: Input signal from IBUF
   .EN_VTC(EN_VTC),                   // 1-bit input: Enable IDELAYCTRL to keep stable delay over VT
   .EN_VTC_EXT(EN_VTC_EXT),           // 1-bit input: Optional extended (cascaded delay) to keep stable
                                      // delay over VT

   .FIFO_RD_CLK(FIFO_RD_CLK),         // 1-bit input: FIFO read clock
   .FIFO_RD_EN(FIFO_RD_EN),           // 1-bit input: FIFO read enable
   .INC(INC),                         // 1-bit input: Increment the current delay tap setting
   .INC_EXT(INC_EXT),                 // 1-bit input: Optional extended (cascaded delay) increments the
                                      // current delay tap setting

   .LOAD(LOAD),                       // 1-bit input: Load the CNTVALUEIN tap setting
   .LOAD_EXT(LOAD_EXT),               // 1-bit input: Optional extended (cascaded delay) load the
                                      // CNTVALUEIN_EXT tap setting

   .RST(RST),                         // 1-bit input: Asynchronous assert, synchronous deassert for
                                      // RX_BITSLICE ISERDES

   .RST_DLY(RST_DLY),                 // 1-bit input: Reset the internal DELAY value to DELAY_VALUE
   .RST_DLY_EXT(RST_DLY_EXT),         // 1-bit input: Optional extended (cascaded delay) reset delay to
                                      // DELAY_VALUE_EXT

   .RX_BIT_CTRL_IN(RX_BIT_CTRL_IN),   // 40-bit input: Input bus from BITSLICE_CONTROL
   .TX_BIT_CTRL_IN(TX_BIT_CTRL_IN)    // 40-bit input: Input bus from BITSLICE_CONTROL
);

// End of RX_BITSLICE_inst instantiation

Related Information

See the UltraScale Architecture SelectIO Resources User Guide (UG571).