ICAPE3 - 2022.1 English

Primitive: Internal Configuration Access Port

PRIMITIVE_GROUP: CONFIGURATION
PRIMITIVE_SUBGROUP: ICAP
Families: UltraScale, UltraScale+

Introduction

This design element gives you access to the configuration functions of the device from the device fabric. Using this component, commands and data can be written to and read from the configuration logic of the device. Because the improper use of this function can have a negative effect on the functionality and reliability of the device, you should not use this element unless you are very familiar with its capabilities.

Port Descriptions

Port	Direction	Width	Function
AVAIL	Output	1	Availability status of ICAP.
CLK	Input	1	Clock input.
CSIB	Input	1	Active-Low ICAP enable.
I<31:0>	Input	32	Configuration data input bus.
O<31:0>	Output	32	Configuration data output bus.
PRDONE	Output	1	Indicates completion of Partial Reconfiguration.
PRERROR	Output	1	Indicates error during Partial Reconfiguration.
RDWRB	Input	1	Read/Write Select input.

Design Entry Method

Instantiation	Recommended
Inference	No
IP and IP Integrator Catalog	No

Available Attributes

Attribute	Type	Allowed Values	Default	Description
DEVICE_ID	HEX	32'h03628093, 32'h03627093	32'h03628093	Specifies the pre-programmed Device ID value to be used for simulation purposes.
ICAP_AUTO_SWITCH	STRING	"DISABLE", "ENABLE"	"DISABLE"	Enable switch ICAP using sync word.
SIM_CFG_FILE_NAME	STRING	String	"NONE"	Specifies the Raw Bitstream (RBT) file to be parsed by the simulation model.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.

Library UNISIM;
use UNISIM.vcomponents.all;


-- ICAPE3: Internal Configuration Access Port
--         UltraScale
-- Xilinx HDL Language Template, version 2022.1

ICAPE3_inst : ICAPE3
generic map (
   DEVICE_ID => X"03628093",      -- Specifies the pre-programmed Device ID value to be used for simulation
                                  -- purposes.
   ICAP_AUTO_SWITCH => "DISABLE", -- Enable switch ICAP using sync word.
   SIM_CFG_FILE_NAME => "NONE"    -- Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
                                  -- model.
)
port map (
   AVAIL => AVAIL,     -- 1-bit output: Availability status of ICAP.
   O => O,             -- 32-bit output: Configuration data output bus.
   PRDONE => PRDONE,   -- 1-bit output: Indicates completion of Partial Reconfiguration.
   PRERROR => PRERROR, -- 1-bit output: Indicates error during Partial Reconfiguration.
   CLK => CLK,         -- 1-bit input: Clock input.
   CSIB => CSIB,       -- 1-bit input: Active-Low ICAP enable.
   I => I,             -- 32-bit input: Configuration data input bus.
   RDWRB => RDWRB      -- 1-bit input: Read/Write Select input.
);

-- End of ICAPE3_inst instantiation

Verilog Instantiation Template


// ICAPE3: Internal Configuration Access Port
//         UltraScale
// Xilinx HDL Language Template, version 2022.1

ICAPE3 #(
   .DEVICE_ID(32'h03628093),     // Specifies the pre-programmed Device ID value to be used for simulation
                                 // purposes.
   .ICAP_AUTO_SWITCH("DISABLE"), // Enable switch ICAP using sync word.
   .SIM_CFG_FILE_NAME("NONE")    // Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
                                 // model.
)
ICAPE3_inst (
   .AVAIL(AVAIL),     // 1-bit output: Availability status of ICAP.
   .O(O),             // 32-bit output: Configuration data output bus.
   .PRDONE(PRDONE),   // 1-bit output: Indicates completion of Partial Reconfiguration.
   .PRERROR(PRERROR), // 1-bit output: Indicates error during Partial Reconfiguration.
   .CLK(CLK),         // 1-bit input: Clock input.
   .CSIB(CSIB),       // 1-bit input: Active-Low ICAP enable.
   .I(I),             // 32-bit input: Configuration data input bus.
   .RDWRB(RDWRB)      // 1-bit input: Read/Write Select input.
);

// End of ICAPE3_inst instantiation

Related Information

See the UltraScale Architecture Configuration User Guide (UG570).