Primitive: VREF Scan
- PRIMITIVE_GROUP: I/O
- PRIMITIVE_SUBGROUP: INPUT_BUFFER
- Families: UltraScale, UltraScale+
Introduction
The HPIO_VREF component, used with the IBUFE3 or IOBUFE3 buffers, provides access to the VREF scan capability in the HPIO banks.
Port Descriptions
| Port | Direction | Width | Function |
|---|---|---|---|
| FABRIC_VREF_TUNE<6:0> | Input | 7 | VREF tuning input value to allow Vref adjustment. |
| VREF | Output | 1 | Tuned output that connects to all associated IBUFE3 or IOBUFE3 components within an HPIO bank. |
Design Entry Method
| Instantiation | Yes |
| Inference | No |
| IP and IP Integrator Catalog | No |
Available Attributes
| Attribute | Type | Allowed Values | Default | Description |
|---|---|---|---|---|
| VREF_CNTR | STRING | "OFF", "FABRIC_RANGE1", "FABRIC_RANGE2" | "OFF" | Specifies VREF counter range. |
VHDL Instantiation Template
Unless they already exist, copy the following
two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- HPIO_VREF: VREF Scan
-- UltraScale
-- Xilinx HDL Language Template, version 2022.1
HPIO_VREF_inst : HPIO_VREF
generic map (
VREF_CNTR => "OFF" -- FABRIC_RANGE1, FABRIC_RANGE2, OFF
)
port map (
VREF => VREF, -- 1-bit output: Tuned output (connect to associated IBUFE3
-- component)
FABRIC_VREF_TUNE => FABRIC_VREF_TUNE -- 7-bit input: VREF tuning value
);
-- End of HPIO_VREF_inst instantiation
Verilog Instantiation Template
// HPIO_VREF: VREF Scan
// UltraScale
// Xilinx HDL Language Template, version 2022.1
HPIO_VREF #(
.VREF_CNTR("OFF") // FABRIC_RANGE1, FABRIC_RANGE2, OFF
)
HPIO_VREF_inst (
.VREF(VREF), // 1-bit output: Tuned output (connect to associated IBUFE3
// component)
.FABRIC_VREF_TUNE(FABRIC_VREF_TUNE) // 7-bit input: VREF tuning value
);
// End of HPIO_VREF_inst instantiation
Related Information
- See the UltraScale Architecture SelectIO Resources User Guide (UG571).