Introduction - 2022.1 English

Vivado Design Suite User Guide: Using the Vivado IDE (UG893)

Document ID
Release Date
2022.1 English

The Vivado® Integrated Design Environment (IDE) provides an intuitive graphical user interface (GUI) with powerful features. All of the tools and tool options are written in native tool command language (Tcl) format, which enables use both in the Vivado IDE or Vivado® Design Suite Tcl shell. Analysis and constraint assignment is enabled throughout the entire design process. For example, you can run timing or power estimations after synthesis, placement, or routing. Because the database is accessible through Tcl, changes to constraints, design configuration or tool settings happen in real time, often without forcing re-implementation.

You can improve design performance using the new algorithms delivered by the Vivado IDE, including:

  • Register transfer level (RTL) design in VHDL, Verilog, and SystemVerilog
  • Intellectual property (IP) integration for cores
  • Behavioral, functional, and timing simulation with Vivado simulator
  • Vivado synthesis
  • Vivado implementation for place and route
  • Vivado serial I/O and logic analyzer for debugging
  • Vivado power analysis
  • SDC-based Xilinx® design constraints (XDC) for timing constraints entry
  • Static timing analysis
  • High-level floorplanning
  • Detailed placement and routing modification
  • Bitstream generation

The Vivado IDE uses a concept of opening designs in memory. Opening a design loads the design netlist at that particular stage of the design flow, assigns the constraints to the design, and then applies the design to the target device. This provides the ability to visualize and interact with the design at each design stage.

You can experiment with different implementation options, refine timing constraints, explore the Vivado IP catalog, perform simulation, and apply physical constraints with floorplanning techniques to help improve design results. Early estimates of resource utilization, interconnect delay, power consumption, and routing connectivity can assist with appropriate logic design, device selection, and floorplanning. As the design moves through the implementation flow, you can further refine the design.

Important: The Vivado IDE supports designs that target 7 series and newer devices only.
Training: To help you learn more about the concepts presented in this document, you can attend the Designing FPGAs Using the Vivado Design Suite 1, Designing FPGAs Using the Vivado Design Suite 2, Designing FPGAs Using the Vivado Design Suite 3, and Designing FPGAs Using the Vivado Design Suite 4 Training Courses.