Input Files - 2022.1 English

Vivado Design Suite User Guide: Using the Vivado IDE (UG893)

Document ID: UG893
Release Date: 2022-04-27
Version: 2022.1 English

Table 1. Vivado IDE Input Files
Input File	File Type	Description
Design Source Files	VHDL Verilog Verilog Header SystemVerilog	You can import and elaborate files to analyze the logic or modify the source. The original source files can be referenced and left in place, or they can be copied into the project for portability. You can specify directories when importing RTL source files. All recognized files and file types contained in the directories are imported into the project.
I/O Port Lists	CSV	You can import a Comma Separated Values (CSV) format file to populate the I/O Ports window within the I/O Planning layout. This functionality is intended for use in an I/O Planning project only. You can assign the I/O ports to physical package pins to define the device pin configuration. CSV is a standard file format used to exchange information with board designers about device pins and pinout.
Module-Level Netlists and Cores	EDIF NGC NGO	The Vivado® IDE can construct a design using multiple EDIF or NGC netlists supporting a hierarchical design methodology. When you select the top-level logic, lower-level modules are imported automatically. This process has more flexibility when updating the design. The Vivado IDE incremental netlist import capability allows netlist updates at any level of the design hierarchy. Note: NGC format files are not supported in the Vivado Design Suite for UltraScale™ devices. Xilinx recommends that you regenerate the IP using the Vivado Design Suite IP customization tools with native output products. Alternatively, you can use the NGC2EDIF command to migrate the NGC file to EDIF format for importing, as described in the ISE to ISE to Vivado Design Suite Migration Guide (UG911). However, Xilinx recommends using native Vivado IP rather than XST-generated NGC format files going forward.
Top-Level Netlists	EDIF NGC	The Vivado IDE supports importing EDIF or NGC netlists. The Vivado IDE can construct the design hierarchy using multiple netlists. When you select the top-level logic, lower-level modules are imported automatically. Incremental netlist import capabilities allow netlist updates at any level of design hierarchy. In-process floorplanning constraints are maintained through iterations.
Xilinx IP and IP Integrator Block Designs	XCI XCIX BD	The Vivado IDE supports importing configured Xilinx IP by using the IP XCI file or the core container XCIX file. The Vivado IDE supports importing a BD file containing a block design created with Vivado IP integrator.
Constraint Files	XDC SDC	The Vivado IDE supports Synopsys Design Constraints (SDC) and Xilinx® Design Constraints (XDC) file formats. The Vivado IDE can import multiple constraints files, which allows for separation of physical constraints, I/Os, and timing constraints.
Other Files	BMM ELF MIF COE	BMM: Block RAM Memory Map (BMM) file is a text file that syntactically describes how individual block RAMs make up a contiguous logical data space. ELF: An Executable and Linkable Format (ELF) file is a binary data file that contains an executable CPU code image ready for running on a CPU. MIF: This file describes the memory contents that are used by a core, a cell, or simulation models. COE: This file describes the initial memory and coefficients contents as input for core generation.