Using the Getting Started Page - 2022.1 English

When you open the Vivado IDE, the Getting Started Page appears as shown in the following figure.

Figure 1. Vivado IDE Getting Started Page

The Vivado IDE Getting Started Page assists you with creating and opening projects, running Vivado IDE commands, and viewing documentation as follows:

• Quick Start

  Create Project

  Opens the New Project wizard to guide you through creating various supported project types. You can also use the wizard to import previously created projects from the Synplify tool.

  Open Project

  Opens a browser that enables you to open any Vivado IDE project file (.xpr extension).

  Open Example Project

  Opens the Open Example Project wizard to guide you through creating a project. Following is an example project, including specifying a project name and location, and choosing from a list of valid parts:

  • BFT: Small RTL project

  Below are few designs:

  Configurable MicroBlaze Design Presets

  Vivado IP integrator MicroBlaze™ processor design targeting various Xilinx evaluation boards. The design allows users to configure in three different modes as a MicroController, Real-Time Processor & Application Class processor. You can implement the design in the Vivado Design Suite, export the hardware to the Vitis™ software platform for application code development, and simulate the design in the Vivado Design Suite using a test bench that you supply and an ELF file generated by the Vitis software platform.

  Note: Configurable MicroBlaze is not available by default. It must be installed through Git.

  Configurable Zynq UltraScale+ MPSoC Design

  Zynq® UltraScale+™ MPSoC design targeting various Xilinx evaluation boards. The designs provide the users with memory virtualization, hardware virtualization, memory protection units, and tightly coupled memories that are required for real-time deterministic applications and executing platform OSes. You can implement the design in the Vivado Design Suite, export the hardware to the Vitis software platform for application code development, and simulate the design in the Vivado Design Suite using a test bench that you supply and an ELF file generated by the Vitis software platform.

  Note: Configurable Zynq UltraScale+ MPSoC is not available by default. It must be installed through Git.

  CPU (HDL)

  Large mixed-language RTL project.

  CPU (Synthesized)

  Large synthesized netlist project.

  Wavegen (HDL)

  Small project that includes three embedded IP cores. You can use this design to learn how to use integrated IP cores with Vivado IDE projects.

  Tip: Click Refresh to update the installed designs or download the latest Xilinx® Example designs.
• Tasks

  Manage IP

  Opens or creates an IP project for customizing and managing IP. The Vivado IP catalog displays Xilinx, third-party, or user-created IP, which can be customized to create IP cores for a specified device. You can also view or re-customize existing IP cores and generate output products, including a netlist of the IP standalone.

  Open Hardware Manager

  Opens the Vivado Design Suite hardware manager to connect to a target JTAG cable or board, which enables you to program your design into a device. The Vivado logic analyzer and Vivado serial I/O analyzer features of the tool enable you to debug your design.

  Vivado Store

  The Vivado store, shown in the following figure, consolidates Tcl apps, board files and configurable example designs into a single location. A catalog file maintains the list of all items available in the stores. To update the catalog, click the refresh button for the respective store in the lower left-hand corner. Individual items can be installed or removed. Xilinx delivers a set of board files and example designs and installs, which cannot be uninstalled. This is because if customers are inside a firewall or do not have access to the internet, they should have access to the board files of Xilinx Proprietary Boards.

  Tcl Apps

  An open source repository of Tcl code designed primarily for use with the Vivado Design Suite. The Tcl Store provides access to multiple scripts and utilities contributed from different sources, which solve various issues and improve productivity. For more information, see this link in the Vivado Design Suite User Guide: Using Tcl Scripting (UG894).

  Boards

  A GitHub repository for Xilinx and third-party hosted board files. Using a board file with Vivado can simplify design creation by integrating board level resources into the design environment. For more information about contributing boards, refer to https://github.com/Xilinx/XilinxBoardStore.

  Example Designs

  A GitHub repository comprised of Xilinx and third-party configurable example designs. These designs are intended to demonstrate specific capabilities of the tool and provide a baseline design. For more information about contributing example designs, refer to https://github.com/Xilinx/XilinxCEDStore.