Step 4: Implement the Design - 2022.1 English

Vitis Model Composer Tutorial (UG1498)

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2022.1 English
In this step, you will implement the IP integrator design and generate a bitsteam.
  1. In the Flow Navigator, click Project Manager to return to the Project Manager view.
  2. In the Sources browser in the main workspace pane, a Block Diagram object called design_1 is at the top of the Design Sources tree view.
  3. Right-click this object and select Generate Output Products.

  4. In the Generate Output Products dialog box, click Generate to start the process of generating the necessary source files.
  5. When the generation completes, right-click the design_1 object again, select Create HDL Wrapper, and click OK (and let Vivado manage the wrapper) to exit the resulting dialog box.

    The top level of the Design Sources tree becomes the design_1_wrapper.v file. The design is now ready to be synthesized, implemented, and have an FPGA programming bitstream generated.

  6. In the Flow Navigator, click Generate Bitstream to initiate the remainder of the flow.
  7. Click Yes, and from the launch runs window click OK to generate the synthesis and implementation files.
  8. In the dialog that appears after bitstream generation has completed, select Open Implemented Design and click OK.
  9. After you view your implemented design, exit the Vivado IDE.