Configure the HDL Blocks - 2022.1 English

Vitis Model Composer Tutorial (UG1498)

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2022.1 English
The first task is to define the coefficients of the new filter. For this task you will use the Xilinx block version of FDATool. If you open the existing FDATool block, you can review the existing Frequency and Magnitude specifications.
  1. Double-click the Digital Filter Design instance to open the Properties Editor.

    This allows you to review the properties of the existing filter.

  2. Close the Properties Editor for the Digital Filter Design instance.
  3. Double-click the FDATool instance to open the Properties Editor.

  4. Change the filter specifications to match the following values:
    • Frequency Specifications
      • Units = MHz
      • Fs = 20
      • Fpass = 1.5
      • Fstop = 8.5
    • Magnitude Specifications
      • Units = dB
      • Apass = 0.01
      • Astop = 100
  5. Click the Design Filter button at the bottom and close the Properties Editor.

    Now, associate the filter parameters of the FDATool instance with the Digital FIR Filter instance.

  6. Double-click the Digital FIR Filter instance to open the Properties Editor.
  7. In the Filter Parameters section, replace the existing coefficients (Coefficient Vector) with xlfda_numerator('FDATool') to use the coefficients defined by the FDATool instance.

  8. Click OK to exit the Digital FIR Filter Properties Editor.

    In an FPGA, the design operates at a specific clock rate and using a specific number of bits to represent the data values.

    The transition between the continuous time used in the standard Simulink environment and the discrete time of the FPGA hardware environment is determined by defining the sample rate of the Gateway In blocks. This determines how often the continuous input waveform is sampled. This sample rate is automatically propagated to other blocks in the design by Vitis Model Composer. In a similar manner, the number of bits used to represent the data is defined in the Gateway In block and also propagated through the system.

    Although not used in this tutorial, some HDL blocks enable rate changes and bit-width changes, up or down, as part of this automatic propagation. More details on these blocks are found in the Vitis Model Composer User Guide (UG1483).

    Both of these attributes (rate and bit width) determine the degree of accuracy with which the continuous time signal is represented. Both of these attributes also have an impact on the size, performance, and hence cost of the final hardware.

    Vitis Model Composer allows you to use the Simulink environment to define, simulate, and review the impact of these attributes.

  9. Double-click the Gateway In block to open the Properties Editor.

    Because the highest frequency sine wave in the design is 9 MHz, sampling theory dictates the sampling frequency of the input port must be at least 18 MHz. For this design, you will use 20 MHz.

  10. At the bottom of the Properties Editor, set the Sample Period to 1/20e6.
  11. For now, leave the bit width as the default fixed-point 2’s complement 16-bits with 14-bits representing the data below the binary point. This allows us to express a range of -2.0 to 1.999, which exceeds the range required for the summation of the sine waves (both of amplitude 1).

  12. Click OK to close the Gateway In Properties Editor.

    This now allows us to use accurate sample rate and bit-widths to accurately verify the hardware.

  13. Double-click the System Generator token to open the Properties Editor.

    Because the input port is sampled at 20 MHz to adequately represent the data, you must define the clock rate of the FPGA and the Simulink sample period to be at least 20 MHz.

  14. Select the Clocking tab.
    1. Specify an FPGA clock period of 50 ns (1/20 MHz).
    2. Specify a Simulink system period of 1/20e6 seconds.
    3. From the Perform analysis menu, select Post Synthesis and from the Analyzer type menu select Resource as shown in the following figure. This option gives the resource utilization details after completion.

  15. Click OK to exit the System Generator token.
  16. Click the Run simulation button to simulate the design and view the results, as shown in the following figure.

    Because the new design is cycle and bit accurate, simulation might take longer to complete than before.

    The results are shown above, on the right hand side (in the Spectrum Analyzer HDL window), and differ slightly from the original design (shown on the left in the Spectrum Analyzer FDA Tool window). This is due to the quantization and sampling effect inherent when a continuous time system is described in discrete time hardware.

    The final step is to implement this design in hardware. This process will synthesize everything contained between the Gateway In and Gateway Out blocks into a hardware description. This description of the design is output in the Verilog or VHDL Hardware Description Language (HDL). This process is controlled by the System Generator token.

  17. Double-click the System Generator token to open the Properties Editor.
  18. Select the Compilation tab to specify details on the device and design flow.
  19. From the Compilation menu, select the IP catalog compilation target to ensure the output is in IP catalog format. The Part menu selects the FPGA device. For now, use the default device. Also, use the default Hardware description language, VHDL.

  20. Click Generate to compile the design into hardware.

    The compilation process transforms the design captured in Simulink blocks into an industry standard Register Transfer Level (RTL) design description. The RTL design can be synthesized into a hardware design. A Resource Analyzer window appears when the hardware design description has been generated.

    The Compilation status dialog box also appears.

  21. Click OK to dismiss the Compilation status dialog box.
  22. Click OK to dismiss the Resource Analyzer window.
  23. Click OK to dismiss the System Generator token.
The final step in the design process is to create the hardware and review the results.