Step 1: Timing Analysis in Vitis Model Composer - 2022.1 English

Vitis Model Composer Tutorial (UG1498)
Document ID
UG1498
Release Date
2022-07-25
Version
2022.1 English
  1. Invoke Vitis Model Composer.
    • On Windows systems select Windows > Xilinx Design Tools > Vitis Model Composer 2021.2.
    • On Linux systems, type model_cpomposer at the command prompt.
  2. Navigate to the Lab3 folder: \HDL_Library\Lab3.

    You can view the directory contents in the MATLAB® Current Folder browser, or type ls at the command line prompt.

  3. Open the Lab3 design using one of the following:
    • At the MATLAB command prompt, type open Lab3.slx
    • Double-click Lab3.slx in the Current Folder browser.

    The Lab3 design opens, as shown in the following figure.



  4. From your Simulink project worksheet, select Simulation > Run or click the Run simulation button to simulate the design.
    Note: In order to see accurate results from Resource Analyzer Window it is recommended to specify a new target directory rather than use the current working directory.
  5. Double-click the System Generator token to open the Properties Editor.
  6. Select the Clocking tab.
  7. From the Perform analysis menu, select Post Synthesis and from Analyzer type menu select Timing as shown in the following figure.

  8. In the System Generator token dialog box, click Generate.

    When you generate, the following occurs:

    1. Vitis Model Composer generates the required files for the selected compilation target. For timing analysis Vitis Model Composer invokes Vivado in the background for the design project, and passes design timing constraints to Vivado.
    2. Depending on your selection for Perform Analysis (Post Synthesis or Post Implementation), the design runs in Vivado through synthesis or through implementation.
    3. After the Vivado tools run is completed, timing paths information is collected and saved in a specific file format from the Vivado timing database.
    4. Vitis Model Composer processes the timing information and displays a Timing Analyzer table with timing paths information as shown in the following figure.


  9. In the timing analyzer table:
    • Paths with lowest slack values display, with the worst slack showing at the top and increasing toward the bottom.
    • Paths with timing violations have a negative slack and display in red.
  10. Cross probe from the Timing Analyzer table to the Simulink model by clicking any path in the Timing Analyzer table, which highlights the corresponding Vitis Model Composer HDL blocks in the model. This allows you to troubleshoot timing violations by analyzing the path on which they occur.
  11. When you cross probe, you see the corresponding path as shown in the following figure.
  12. Blocks with timing violations are highlighted in red.

  13. Double-click the second path in the Timing Analyzer table and cross-probe, the corresponding highlighted path in green which indicates no timing violation.