Objectives
After completing this lab, you will be able to:
- Create a Finite State Machine using the MCode block in Vitis Model Composer.
- Import an RTL HDL description into Vitis Model Composer.
- Configure the black box to ensure the design can be successfully simulated.
- Incorporate a design, synthesized from C, C++ or SystemC using Vitis HLS, as a block into your MATLAB design.