Lab 6: Using a Vitis Model Composer HDL Design with a Zynq-7000 SoC - 2022.1 English

Vitis Model Composer Tutorial (UG1498)

Document ID
UG1498
Release Date
2022-07-25
Version
2022.1 English

In this lab, you will learn how to export your Vivado® design with Vitis Model Composer HDL IP to a software environment and use driver files created by Vitis Model Composer to quickly implement your project on a Xilinx® evaluation board, running hardware with software in the same design.

Objectives

After completing this lab, you will have learned:

  • How to export your Vivado design with Vitis Model Composer HDL IP to a software environment ( Vitis™ software platform).
  • How Vitis Model Composer automatically creates software driver files for AXI4-Lite interfaces.
  • How to integrate the Vitis Model Composer driver files into your software application.

Procedure

This lab has two primary parts:

  • In Step 1, you will review the AXI4-Lite interface and associated C drivers.
  • In Step 2, you will export your Vivado design to a Vitis software environment and run it on a board.