Vitis Model Composer
can generate graph code from your design. It also generates a make file and collects
data from the input and output port of your system. In this step you will see how this
is done.
- Create a subsystem from all three blocks in your design. You can do this by
selecting the blocks and clicking the Create Subsystem
button as shown in the following figure.
- Assign a name to the subsystem, for example
aie_system. - Drag the Model Composer Hub from the library browser or simply click on the
canvas and start typing
Model Composer Hub.
- Double-click the Model Composer Hub and make changes as follows.
When you check Create testbench, the tool generates a testbench, including input and output test vectors from Vitis Model Composer. You can use AI Engine SystemC Simulator to verify the correctness of the design by comparing the results with the test vectors from Vitis Model Composer.Note: The AIE simulation may take some time to complete. - Click Apply and then Generate and Run. Within a few seconds the code
directory gets created. Because you also checked Create testbench, the aiecompiler will get invoked under the
hood and compile the code using the generated graph code and the kernel source
codes. It subsequently runs the AIE Simulation.
This operation takes some time. Observe the simulation completion message along with the comparison of the output to the Simulink output (data/reference_output/Out1.txt). It prints any diff, in the wait dialog.
- Click OK to exit the Progress window.
- Navigate to code/src_aie to inspect the generated graph
code and Makefile. The tool automates the generation of all these files.
- Navigate to the data folder and observe the reference_output/ directory where the data logged from Simulink
gets stored. The aiesimulator_output/
folder logs the data from AI Engine SystemC
simulator and Vitis Model Composer compares the results at
the end of simulation.
