Step 1: Review Requirements for Generating Code - 2022.1 English

Vitis Model Composer Tutorial (UG1498)
Document ID
UG1498
Release Date
2022-07-25
Version
2022.1 English
In this step, you review the three requirements to move from your algorithm in Simulink to an implementation through automatic code generation.
  1. In the MATLAB Current Folder, navigate to the \HLS_Library\Lab4 directory.
  2. Double-click CodeGen_start.slx to open the model.

    To prepare for code generation, you will enclose your Vitis Model Composer design in a subsystem.

  3. Right-click the Edge Detection area, and select Create Subsystem from Area.
    Note: For code generation to work, all the blocks within the enclosed subsystem should only be from the Vitis Model Composer HLS library, with the exception of the Simulink blocks noted below. Subsystems with unsupported blocks will generate errors during code generation. The Simulink diagnostic viewer will contain error messages and links to the unsupported blocks in the subsystem.
    Note: In addition to the base Vitis Model Composer HLS blocks, a subset of native Simulink blocks such as From, Goto, Bus Creator, Bus Selector, If, and others, are supported. The supported Simulink blocks appear within the HLS libraries as well.

    Next, you add the Model Composer Hub block at the top level of your design.

  4. Open the Simulink Library Browser and navigate to Xilinx Tool Box > HLS > Tools sub-library.
  5. Find the Model Composer Hub block, and add it into the design as shown in the following figure.

    Next, you use the Model Composer Hub block to select the code generation options for the design.

  6. Double-click the block to open the block interface and set up as shown in the following figure.

  7. On the Code Generation tab, you can set the following options as shown in the previous figure:
    Code directory
    In this case, use ./codegen_edge_detection for the generating code.
    Subsystem name
    In this case, use the Edge Detection subsystem. You can have multiple subsystems at the top-level and use the Model Composer Hub block to select and individually compile the subsystem you want.
    Target
    This option determines what you want to convert your design into. In this case IP Catalog. You can select other compilation targets from the drop-down.
    • Vitis HLS Synthesizable C++ code.
    • System Generator.
    Note: The AI Engines (default) target is not applicable for the HLS block library.
  8. On the Hardware tab, you can specify the target FPGA clock frequency in MHz. The default value is 200 MHz.
  9. Click Apply then OK.