Convert Data Types - 2022.1 English

Vitis Model Composer Tutorial (UG1498)
Document ID
UG1498
Release Date
2022-07-25
Version
2022.1 English
To convert the previous design to use Xilinx Fixed Point types:
Note: Fixed point representation helps to achieve optimal resource usage and performance for a usually acceptable trade-off in precision, depending on the dataset/algorithm.
  1. Double-click ColorSpace_Conversion_fixed_start.slx in the Current Folder to open the design.
  2. Open the HLS library in the Simulink Library Browser.
  3. Navigate to the Signal Attributes sub-library, select the Data Type Conversion block, and drag it into the empty slots in the designs, before and after the RGB to YCbCr subsystem.



  4. Open the Data Type Conversion blocks at the inputs of the RGB to YCbCr Subsystem, and do the following:
    • Change the Output data type parameter to fixed.
    • Set the Signedness to Unsigned.
    • Set the Word length to 8.
    • Set Fractional length to 7.
    • Click Apply, and close the dialog box.

  5. Add the Data Type Conversion blocks at the output of the RGB to YCbCr Subsystem and set the Output data type parameter to single. This will enable connecting the output signals to the Video Viewer blocks for visualization.
  6. Double-click the RGB to YCbCr subsystem to descend the hierarchy and open the model. Within the RGB to YCbCr subsystem, there are subsystems to calculate Y, Cb, and Cr components using Gain and Constant blocks.

    You can control the fixed point types for the gain parameter in the Gain blocks and the value in the Constant blocks. You can do this by opening up the Calculate_Y, Calculate_Cb, and Calculate_Cr blocks and setting the data types as follows.

    For Gain blocks, set the Gain data type to fixed. For Constant blocks, on the Data Types tab set the Output data type to fixed. The following options appear:

    • Signedness to Signed
    • Word length to 8
    • Fractional length to 7
    Tip: You can use the View > Property Inspector command to open the Property Inspector window. When you select the different Gain or Constant blocks, you can see and modify the properties on the selected block.

    Ensure you do this for all the Constant and Gain blocks in the design. Update the model (Ctrl+D) and observe the fixed point data types being propagated along with automatic bit growth in gain blocks and adder trees in the design as shown in the following figure:



The general format used to display the Xilinx fixed point data types is as follows:
  • x_[u/s]fix[wl]_En[fl]
u
Unsigned
s
Signed
wl
Word Length
fl
Fractional Length

For example, x_sfix16_En8 represents a signed fixed point number with Word Length=16 and Fractional Length=8.

You can view a completed version of the design here: ug1498-model-composer-sys-gen-tutorial\HLS_Library\Lab1\Section2\solution\Colorspace_Conversion_fixed.slx