Block RAM Cascade Optimizations - 2021.2 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

Document ID
Release Date
2021.2 English

In Xilinx® 7 series devices, if block RAMs are found to be cascaded, because only one block RAM can be active at any time, the rest of the block RAMs can be disabled based on address and any existing enable conditions. This enables large power savings. These optimizations are performed by default in the opt_design phase in the Vivado® Design Suite.