PCIe - 2021.2 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

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2021.2 English

Versal® ACAP devices have a dedicated PCIe® core in the MAC column, denoted as PCIe. It is a standalone Gen4x8 core without an embedded DMA engine. The core supports Gen1, Gen2, Gen3 and Gen4 line rates. The link widths are x1, x2, x4, x8 or x16 link widths (x16 configuration supported only for Gen1-3 speeds). The combination of PCIe® block, block RAMs/UltraRAMs, GTs, and fabric clocking implements all three layers of the PCI Express protocol, which are the physical layer, data link layer and transaction layer. PCIe Power is reported under the Hard IP's section. For more information, see Versal ACAP Integrated Block for PCI Express LogiCORE IP Product Guide (PG343).

Figure 1. PCIe View