Supported Inputs - 2021.2 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

Document ID
Release Date
2021.2 English
  • XDC constraints file to specify timing constraints.
  • Simulation output activity file results from behavioral or timing simulation results (SAIF files).
  • XDC/Tcl file commands to specify environment, operating conditions, tool defaults, and individual netlist nodes activity. For UltraScale+™ devices, XPE dumps the XDC files that are sourced from Vivado® Integrated Design Environment.
  • The Vivado power analysis tool has multiple mechanisms to enter default values and node activity rates. The list below presents the different mechanisms; the list is sorted from highest priority to lowest.
    1. Static (constant tied to GND or VCC).
    2. User entered value in any of the Utilization Details views in the Power Results window.
    3. Imported simulation activity file (SAIF).
    4. Imported constraint files – Clock constraints imported from constraint files (XDC) or the design netlist.
    5. Vectorless estimation – For any node not defined in any of the previously listed inputs, the vectorless estimation will try to estimate activity based on default values combined with the activity of inputs to the node.
    6. A default value – For nodes that cannot be estimated by the vectorless estimation a default is assigned, as in the case of design primary inputs and black box outputs.
Note: You can adjust default values in the Report Power dialog box. See Review Device/Design Settings and Adjust Activity for Known Elements for more information.