Setting Power Optimization Constraints - 2021.2 English

Vivado Design Suite User Guide: Power Analysis and Optimization (UG907)

Document ID
Release Date
2021.2 English

Prior to running power optimization, you can optionally set power optimization constraints to identify portions of the design that need to be optimized for power. The set_power_opt command provides you the option to include or exclude cell types, hierarchy levels or clock domains for power optimization.

Tip: You need to use the power_opt_design command to enable the power optimization step. The set_power_opt command is used only for targeting the optimization.

The syntax for the set_power_opt command is:

set_power_opt [-include_cells <args>] [-exclude_cells <args>] [-clocks <args>] [-cell_types <args>] [-quiet] [-verbose]
Table 1. set_power_opt Options
Option Name Optional Default Description
-include_cells Yes All Include only the listed cells for clock gating
-exclude_cells Yes None Exclude the listed cells from clock gating
-clocks Yes All clocks Clock gate the cells clocked by the listed clocks only
-cell_types Yes All Clock gate the following cell types only: [all|bram|uram|reg|srl|none]
-quiet Yes N/A Ignore command errors
-verbose Yes N/A Suspend message limits during command execution


The following example sets power optimization for block RAM and REG type cells, then adds SRLs:

set_power_opt -cell_types {bram reg}
set_power_opt -cell_types {srl}

The following example sets power optimization for block RAM cells only, then excludes the cpuEngine block from optimization, but then includes the cpuEngine/cpu_dbg_dat_i block:

set_power_opt -cell_types bram
set_power_opt -exclude_cells cpuEngine
set_power_opt -include_cells cpuEngine/cpu_dbg_dat_i