Vivado implementation focuses on the most
critical paths first, which often makes less difficult paths become critical after
placement or after routing. Xilinx recommends
identifying and improving the longest paths after synthesis or after opt_design, because it will have the biggest impact on
timing and power QoR and will usually dramatically reduce the number of place and route
iterations to reach timing closure.
Before placement, timing analysis uses estimated delays that correspond to ideal
placement and typical clock skew. By using report_timing, report_timing_summary, or
report_design_analysis, you can quickly identify the
paths with too many logic levels or with high cell delays, because they usually fail
timing or barely meet timing before placement. Use the methodology proposed in Identifying Timing Violations Root Cause to find the long paths which need to be improved before
implementing the design.