SystemC is a C++ library that enables hardware modeling. This library provides structural elements, such as modules, ports, and interfaces, as well as data types. In addition to cycle-accurate simulation models, Xilinx provides fast, transaction-accurate, SystemC simulation models for some Versal ACAP infrastructure blocks for use in Vitis hardware emulation flows. SystemC models allow faster simulation compared to RTL models, which helps to reduce overall simulation time.
In general, SystemC models are used for performance analysis, architecture exploration, DMA synchronization, and address trace generation and performance modeling. However, Xilinx recommends using RTL models when accuracy and debugging are more important, such as with DMA transaction or timing dependent issues.
| Block | Cycle Accurate | Performance |
|---|---|---|
| PS |
QEMU (functional only) |
QEMU (functional only) CIPS Verification IP (VIP) |
| NoC | Behavioral SystemVerilog (cycle approximate) | SystemC |
| DDRMC | Behavioral SystemVerilog | SystemC |
| PL-based soft memory controller | Behavioral SystemVerilog | Behavioral SystemVerilog |
| GT | Behavioral SecureIP | File I/O (for Vitis software platform users only) |
| GT-based IP | Behavioral SecureIP | AXI verification IP File I/O (for Vitis software platform users only) |
| HLS-based IP | RTL | RTL |
| Other IP | Varies by IP | Varies by IP |
| PL | Behavioral Verilog VHDL SystemVerilog |
Behavioral Verilog VHDL SystemVerilog |
| AI Engine | SystemC | SystemC |