When analyzing system performance in simulation, the critical data paths are between the AI Engines, PL, NoC (DDR), and high-speed transceivers. Before the system is integrated, you must ensure that each block meets its performance estimates.
Note: For traditional designs without a platform for use in the Vitis tools, system performance analysis is based on RTL simulation and
hardware debug features, such as
ChipScope™
debug IP cores and
dedicated hard block debug features.