Checking for Valid Constraints - 2021.2 English

Review the Check Timing section of the Timing Summary report to quickly assess the timing constraints coverage, including the following:

• All active clock pins are reached by a clock definition.
• All active path endpoints have requirement with respect to a defined clock (setup/hold/recovery/removal).
• All active input ports have an input delay constraint.
• All active output ports have an output delay constraint.
• Timing exceptions are correctly specified.
  CAUTION:
  Excessive use of wildcards in constraints can cause the actual constraints to be different from what you intended. Use the report_exceptions command to identify timing exception conflicts and to review the netlist objects, timing clocks, and timing paths covered by each exception.

In addition to check_timing, the Methodology report (TIMING and XDC checks) flags timing constraints that can lead to inaccurate timing analysis and possible hardware malfunction. You must carefully review and address all reported issues.