USB 3.0 - 2021.2 English

Zynq UltraScale+ MPSoC Software Developer Guide

Document ID
Release Date
2021.2 English

The Zynq UltraScale+ MPSoC USB 3.0 controller consists of two independent dual-role device (DRD) controllers. Both can be individually configured to work as host or device at any given time. The USB 3.0 DRD controller provides an eXtensible host controller interface (xHCI) to the system software through the advanced eXtensible interface (AXI) slave interface.

  • An internal DMA engine is present in the controller and it uses the AXI master interface to transfer data.
  • The three dual-port RAM configurations implement the RX data FIFO, TX data FIFO, and the descriptor/register cache.

The following flow diagrams illustrate how to configure USB as mass storage device.

Figure 1. USB Example Flow: USB Initialization
Figure 2. Example USB Flow: Hookup Bulk in and Bulk out Handlers and Initialize Interrupt Controller
Figure 3. Enable Interrupts and Start the USB Controller

For more information on USB controller, see this link to the “USB 2.0/3.0 Host, Device, and Controller,” chapter of the Zynq UltraScale+ Device Technical Reference Manual (UG1085).