PMU Firmware Signals PLL Lock Errors on PS_ERROR_OUT - 2021.2 English

Zynq UltraScale+ MPSoC Software Developer Guide

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2021.2 English

When EM module is enabled, it is recommended to enable SCHEDULER also. During FSBL execution of psu_init, it is expected to get the PLL lock errors. To avoid these errors during EM module initialization, PMU firmware will not enable PLL Lock errors. It waits for psu_init completion by FSBL using a scheduler task. After FSBL completes execution of psu_init, PMU firmware will enable all PLL Lock errors.

In xpfw_error_management.c, you can see the following default behavior of the PMU firmware for PLL Lock Errors:

[EM_ERR_ID_PLL_LOCK] = { .Type = EM_ERR_TYPE_2, .RegMask =

where, PMU_GLOBAL_ERROR_STATUS_2_PLL_LOCK_MASK is #defined with 0X00001F00 value, which means that all the PLL Lock Errors are enabled. Hence, if the design do not use any PLL/PLLs that are not locked, this triggers the PS_ERROR_OUT signal. It means that the PMU_GLOBAL.ERROR_STATUS_2 register (bits [12:8]) signals that one or more PLLs are NOT locked and that triggers the PS_ERROR_OUT signal.

To analyze further and see if this is really an issue is to fully understand the status of the PLL in the design. For example, if the design only uses IO_PLL and DDR_PLL and PMU_GLOBAL.ERROR_STATUS_2 register signals 0x1600 value, it means that the RPU_PLL, APU_PLL, and Video_PLL Lock errors have occurred. Looking at a few more registers, you can really understand the status of the PLLs.


  • PLL_STATUS (CRL_APB) = FF5E0040: 00000019
  • PLL_STATUS (CRF_APB) = FD1A0044: 0000003A
IOPLL is locked and stable Bit [8] is for IO_PLL = 0
RPLL is stabled and NOT locked (which means bypassed) Bit [9] is for RPU_PLL = 1
APPL is stabled and NOT locked (which means bypassed) Bit [10] is for APU_PLL = 1
DPLL is locked and stable Bit [11] is for DDR_PLL = 0
VPLL is stabled and NOT locked (which means bypassed) Bit [12] is for Video_PLL = 1

Hence, if the design only uses IO_PLL and DDR_PLL, then it is not really an error to have RPU_PLL, APU_PLL and Video_PLL in NOT locked status.

Xilinx recommends you to customize the PMU_GLOBAL_ERROR_STATUS_2_PLL_LOCK_MASK to cover only the PLL of interest so that you can have a meaningful PS_ERROR_OUT signal.


#define PMU_GLOBAL_ERROR_STATUS_2_PLL_LOCK_MASK ((u32)0X00000900U) will only
signal on PS_ERROR_OUT IO_PLL and DDR_PLL errors.